diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala
index 838f6f0..2e50e20 100644
--- a/src/main/scala/backBoard/shin/SMUnit.scala
+++ b/src/main/scala/backBoard/shin/SMUnit.scala
@@ -8,6 +8,8 @@ class SMUnitIO extends Bundle {
   val enq = Flipped(Decoupled(UInt(8.W)))
   val deq = Decoupled(UInt(8.W))
 
+  val sram = Vec(4, new SRAM2kIO)
+
 }
 
 abstract class SMUnitBase extends Module {
@@ -21,10 +23,14 @@ abstract class SMUnitBase extends Module {
 
 
   val dataBuf =
-    for ( _ <- until 4 ) yield {
-      Module( new Queue(UInt(8.W), 2048, useSyncReadMem = true) )        
+    for ( i <- 0 until 4 ) yield {
+      val mdl = Module( new SRAM2kFifo )
+      io.sram(i) <> mdl.io.sram
+      mdl
     }
 
+  
+
   val wPtr = RegInit(0.U((2+1).W))
   val rPtr = RegInit(0.U((2+1).W))
 
diff --git a/src/main/scala/backBoard/shin/SRAMFifo.scala b/src/main/scala/backBoard/shin/SRAMFifo.scala
new file mode 100644
index 0000000..93c65d3
--- /dev/null
+++ b/src/main/scala/backBoard/shin/SRAMFifo.scala
@@ -0,0 +1,52 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class SRAM2kIO extends Bundle {
+  val addrr  = Output(UInt(11.W))
+  val addrw  = Output(UInt(11.W))
+
+  val dataw = Output( UInt(8.W) )
+  val datar = Input( UInt(8.W) )
+  val enw   = Output(Bool())
+  val enr   = Output(Bool())
+}
+
+class SRAM2kFifoIO extends Bundle {
+  val sram = new SRAM2kIO
+
+  val enq = Flipped(Decoupled(UInt(8.W)))
+  val deq = Decoupled(UInt(8.W))
+}
+
+class SRAM2kFifo extends Module {
+  val io: SRAM2kFifoIO = IO(new SRAM2kFifoIO)
+
+  val wptr = RegInit(0.U((11+1).W))
+  val rptr = RegInit(0.U((11+1).W))
+
+  val isFull  = (wptr.extract(11) =/= rptr.extract(11)) & (wptr(10,0) === rptr(10,0))
+  val isEmpty = (wptr === rptr)
+
+
+  io.sram.addrr := rptr(10,0)
+  io.sram.addrw := wptr(10,0)
+
+  io.sram.dataw := io.enq.bits
+  io.deq.bits := io.sram.datar
+  io.sram.enw   := io.enq.fire
+  io.sram.enr   := true.B
+
+  io.enq.ready := ~isFull
+  io.deq.valid := ~isEmpty
+
+  when( io.enq.fire ){
+    wptr := wptr + 1.U
+  }
+
+  when( io.deq.fire ){
+    rptr := rptr + 1.U
+  }
+
+}