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修改测试方案

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This commit is contained in:
bacon
2025-09-07 07:37:34 +08:00
parent 3678b24318
commit 1958f196f5
12 changed files with 75 additions and 50 deletions
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2
ShinRelease.sh
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@@ -12,6 +12,8 @@ cp -r ./src/main/resources ${TARGET_DIR}/
cp ./tb/shinTest/Makefile_vcs ${TARGET_DIR}/Makefile
cp ./tb/shinTest/shinTest_vcs.f ${TARGET_DIR}/
cp ./tb/shinTest/shinTestClk_vcs.f ${TARGET_DIR}/
find ./generated/shin -name *.v >> ${TARGET_DIR}/shinTest_vcs.f
find ./generated/shin -name *.v >> ${TARGET_DIR}/shinTestClk_vcs.f
#awk '{gsub(/.\/tb\/build\/wave.vcd/, "./generated/wave.vcd"); print }' ../RISCV-MAC-SWICH/tb/shinTest/ShinTopSpiTb.v > ./shinTest/ShinTopSpiTb.v
awk '{gsub(/tb\/shinTest\/testcase_result/, "./shinTest/testcase_result"); print }' ./tb/shinTest/check_testcase.py > ${TARGET_DIR}/shinTest/check_testcase.py
#awk '{gsub(/.\/tb\/build\/wave_clk.vcd/, "./generated/wave_clk.vcd"); print }' ../RISCV-MAC-SWICH/tb/shinTest/ShinTopSpiTb_clk.v > ./shinTest/ShinTopSpiTb_clk.v

4
tb/shinTest/Makefile_vcs
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@@ -1,6 +1,7 @@
.PHONY:com sim clean
OUTPUT = shin_test
CPU_COUNT := $(shell nproc)
VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
-full64 \
@@ -8,6 +9,7 @@ VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
-l compile.log \
-debug_access+none \
+define+VCS_COMPILE \
-fastpartcomp=j$(nproc) \
SIM = ./${OUTPUT} -l run.log
@@ -15,10 +17,12 @@ testShin_vcs:
python3 ./shinTest/gen_pkt.py
mkdir -p generated/log
rm -rf generated/log/*
@echo "Available CPUs: ${CPU_COUNT}"
${VCS} -f ./shinTest_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
testShinClk_vcs:
python3 ./shinTest/gen_pkt_clk.py
mkdir -p generated/log

2
tb/shinTest/ShinTopSpiTb.v
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@@ -170,7 +170,7 @@ ShinTop s_ShinTop_Mst(
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
.io_uniCode(64'h0)
);
`include "slave_dev_def.vh"

2
tb/shinTest/ShinTopSpiTb_clk.v
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@@ -145,7 +145,7 @@ ShinTop s_ShinTop_Mst(
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
.io_uniCode(64'h0)
);
`include "slave_dev_def.vh"

4
tb/shinTest/check_testcase.py
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@@ -40,6 +40,7 @@ def parse_value(value):
return parsed_value, mask
def compare_files(source_file, target_file):
warning_need_recheck = 0
try:
with open(source_file, 'r') as src, open(target_file, 'r') as tgt:
source_lines = src.readlines()
@@ -62,6 +63,9 @@ def compare_files(source_file, target_file):
continue
else:
if src_values[0].strip().lower() == 'x':
if warning_need_recheck == 0:
print(f'[\033[93mWARNING\033[0m] Ignored lines detected. This test case requires manual comparison. \n\t[\033[93mTARGET\033[0m] {target_file}\t[\033[93mSRC\033[0m] {source_file}')
warning_need_recheck = 1
continue
line_match = True

2
tb/shinTest/pyutils/GenPkt.py
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@@ -318,7 +318,7 @@ def genSlvSMWriteData(dev, sm, data_len, data = None, wlog=True):
code = '''txBuf[3] = 8'h%02x;\n'''%(data_len & 0xff, )\
+ '''txBuf[4] = 8'h%02x;\n'''%(int(data_len/256) & 0xff,)\
+ '''%s((16'h0%04x), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", smaddr[sm], dev)
+ '''%s((16'h%04x), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%("`SPI_TRANS" if wlog else "spi_trans", smaddr[sm], dev)
for i in range(data_len):
code = code + '''txBuf[%d + 3] = 8'h%02x;\n'''%(i, data[i])

22
tb/shinTest/shinTestClk_vcs.f
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@@ -1,24 +1,2 @@
+incdir+./generated/shin
./shinTest/ShinTopSpiTb_clk.v
./generated/shin/b4b5DualDecode.v
./generated/shin/b4b5DualEncode.v
./generated/shin/b8b10Decode.v
./generated/shin/b8b10Encode.v
./generated/shin/CDRInAxis.v
./generated/shin/CDRInMultiSample.v
./generated/shin/CDROut.v
./generated/shin/crc32_8.v
./generated/shin/Interface.v
./generated/shin/MasterParser.v
./generated/shin/MstSlvSwitch.v
./generated/shin/QSpiInterface.v
./generated/shin/Queue_4.v
./generated/shin/Queue.v
./generated/shin/ShareSRAM2k.v
./generated/shin/ShinTop.v
./generated/shin/SlaveParser.v
./generated/shin/SlaveRecParser.v
./generated/shin/SlaveSendGen.v
./generated/shin/SMUnit_4.v
./generated/shin/SMUnit.v
./generated/shin/SSpiInterface.v

24
tb/shinTest/shinTest_vcs.f
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@@ -1,24 +1,2 @@
+incdir+./generated/shin
./shinTest/ShinTopSpiTb_clk.v
./generated/shin/b4b5DualDecode.v
./generated/shin/b4b5DualEncode.v
./generated/shin/b8b10Decode.v
./generated/shin/b8b10Encode.v
./generated/shin/CDRInAxis.v
./generated/shin/CDRInMultiSample.v
./generated/shin/CDROut.v
./generated/shin/crc32_8.v
./generated/shin/Interface.v
./generated/shin/MasterParser.v
./generated/shin/MstSlvSwitch.v
./generated/shin/QSpiInterface.v
./generated/shin/Queue_4.v
./generated/shin/Queue.v
./generated/shin/ShareSRAM2k.v
./generated/shin/ShinTop.v
./generated/shin/SlaveParser.v
./generated/shin/SlaveRecParser.v
./generated/shin/SlaveSendGen.v
./generated/shin/SMUnit_4.v
./generated/shin/SMUnit.v
./generated/shin/SSpiInterface.v
./shinTest/ShinTopSpiTb.v

5
tb/shinTest/testcase/base.py
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@@ -2484,6 +2484,11 @@ def tc29():
genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)
+genMessageCode("--清除中断")
+genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+genIFRwDataCode(1, 0x180, True, 128, list(range(128)))
+genIFRwDataCode(2, 0x180, True, 128, list(range(4, 128 + 4)))
+genIFRwDataCode(3, 0x180, True, 128, list(range(8, 128 + 8)))
+genIFRwDataCode(4, 0x180, True, 128, list(range(16, 128 + 16)))
)
genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)

4
tb/shinTest/testcase/environment.py
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@@ -191,7 +191,7 @@ def __GenDevice(id, TerminateNode = False, diffclk = False):
multiclk = "multiCLK2"
code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, )
+"\t.clock(clock),\n"
+"\t.clock(%s),\n"%(clk, )
+"\t.reset(reset | isSoftReset_reg[%d]),\n\n"%(id + 1,)
+"\t.io_multiCLK_0(%s[0]),\n"%(multiclk, )
@@ -238,7 +238,7 @@ def __GenDevice(id, TerminateNode = False, diffclk = False):
+"\t.io_latchPin_0(latch0),\n"
+"\t.io_latchPin_1(latch1),\n"
+"\t.io_hwSerial(`HW_SERIAL),\n"
+"\t.io_uniCode(0)\n"
+"\t.io_uniCode(64'h0)\n"
+"\t);\n\n\n"
)
return code_device

25
tb/shinTest/testcase_result/base_tc29_result.log Normal file
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29
tb/shinTest/testcase_result/base_tc30_result.log Normal file
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File diff suppressed because one or more lines are too long