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CDR基本测试通过

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This commit is contained in:
RuigeLee
2024-09-19 15:23:38 +08:00
parent 57c81d5cac
commit 1368e9037d
5 changed files with 161 additions and 19 deletions
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32
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -53,7 +53,7 @@ trait CDRInAxis{ this: CDRInBase =>
val crcCmp = Reg(UInt(32.W))
val bitCnt = Reg(UInt(3.W))
val byteCnt = Reg(UInt(16.W))
val byteCnt = RegInit(0.U(16.W))
val syncSerDat: Bool
val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
@@ -66,10 +66,10 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext :=
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( (byteCnt === 8.U) & (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 4.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
(stateCurr === STATE_IDLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
))
@@ -88,17 +88,17 @@ trait CDRInAxis{ this: CDRInBase =>
byteCnt := 1.U
} .elsewhen( bitCnt === 7.U ){
when( stateCurr === STATE_IDLE ){
byteCnt := Mux( byteCnt =/= 8.U & shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass
assert( byteCnt <= 8.U )
byteCnt := Mux( byteCnt =/= 7.U & shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass
assert( byteCnt <= 7.U )
} .elsewhen( stateCurr === STATE_HEADER ){
byteCnt := Mux( byteCnt =/= (HeaderByte).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte).U )
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte-1).U )
} .elsewhen( stateCurr === STATE_PAYLOAD ){
byteCnt := Mux( byteCnt =/= payloadLen, byteCnt + 1.U, 0.U )
assert( byteCnt <= payloadLen )
byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
assert( byteCnt <= ( payloadLen-1.U ) )
} .elsewhen( stateCurr === STATE_CRC ){
byteCnt := Mux( byteCnt =/= 4.U, byteCnt + 1.U, 0.U )
assert( byteCnt <= 4.U )
byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U )
assert( byteCnt <= 3.U )
}
}
@@ -110,8 +110,8 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 4.U & (crcOut =/= ~Cat( crcCmp(23,0), shiftData )), bitCnt === 7.U )
val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 4.U, bitCnt === 7.U )
val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 7.U )
val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 7.U )
io.axis.valid := axis_valid
io.axis.bits.tdata := axis_tdata
@@ -126,7 +126,7 @@ trait CDRInAxis{ this: CDRInBase =>
}
when( stateCurr === STATE_CRC & bitCnt === 7.U ){
crcCmp := Cat( crcCmp(23,0), shiftData )
crcCmp := Cat( shiftData, crcCmp(31,8) )
}