compile without tl2cdr
This commit is contained in:
Ruige Lee (WSL)
@@ -1,194 +1,195 @@
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package BACK
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package BACK
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import chisel3._
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import chisel3._
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import chisel3.util._
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import chisel3.util._
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//work in 100MHZ
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//work in 100MHZ
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class CDRInIO extends Bundle{
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class CDRInIO extends Bundle{
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val axis = Decoupled(new AXIS_Bundle(8))
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val axis = Decoupled(new AXIS_Bundle(8))
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val serDat = Input(Bool())
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val serDat = Input(Bool())
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val overCLK = Input(Bool())
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val overCLK = Input(Bool())
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}
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}
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abstract class CDRInBase extends Module{
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abstract class CDRInBase extends Module{
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def sampleRate: Int = 4
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def sampleRate: Int = 4
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require( sampleRate == 4 )
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require( sampleRate == 4 )
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val io: CDRInIO = IO(new CDRInIO)
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val io: CDRInIO = IO(new CDRInIO)
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}
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}
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trait CDRInOverSample{ this: CDRInBase =>
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trait CDRInOverSample{ this: CDRInBase =>
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val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
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val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
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// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
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// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
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// val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
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// val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
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// val isArbLock = RegInit(false.B)
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// val isArbLock = RegInit(false.B)
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// for( i <- 0 until sampleRate ){
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// for( i <- 0 until sampleRate ){
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// arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
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// arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
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// when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
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// when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
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// isArbLock := true.B
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// isArbLock := true.B
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// arbSel := i.U
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// arbSel := i.U
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// }
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// }
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// }
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// }
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// when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
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// when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
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// isArbLock := false.B
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// isArbLock := false.B
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// }
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// }
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// val syncSerDat =
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// val syncSerDat =
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// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
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// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
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val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)); arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) ) }
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val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
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val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
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arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) )
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when( sampleReg(0) ^ sampleReg(1) ){
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val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
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arbLock := arbCnt
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when( sampleReg(0) ^ sampleReg(1) ){
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}
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arbLock := arbCnt
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}
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val asyncSerDat = Mux1H(Seq(
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(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
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val asyncSerDat = Mux1H(Seq(
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(arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0),
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(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
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(arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1),
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(arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0),
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(arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2),
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(arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1),
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(arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2),
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(arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2),
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(arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3),
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(arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2),
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(arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0),
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(arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3),
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(arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1),
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(arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0),
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(arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1),
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(arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1),
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(arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2),
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(arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1),
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(arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3),
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(arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2),
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(arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0),
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(arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3),
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(arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0),
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(arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0),
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(arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1),
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(arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0),
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(arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2),
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(arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1),
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(arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3),
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(arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2),
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))
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(arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3),
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))
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val syncSerDat = ShiftRegister( asyncSerDat, 2 )
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val syncSerDat = ShiftRegister( asyncSerDat, 2 )
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}
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}
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trait CDRInAxis{ this: CDRInBase =>
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trait CDRInAxis{ this: CDRInBase =>
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def HeaderByte: Int = 8
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def HeaderByte: Int = 8
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val ETH_PRE = "h55".U(8.W)
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val ETH_SFD = "hD5".U(8.W)
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val ETH_PRE = "h55".U(8.W)
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val ETH_SFD = "hD5".U(8.W)
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val STATE_IDLE = 0.U
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val STATE_HEADER = 1.U
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val STATE_IDLE = 0.U
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val STATE_PAYLOAD = 2.U
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val STATE_HEADER = 1.U
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val STATE_CRC = 3.U
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val STATE_PAYLOAD = 2.U
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val STATE_CRC = 3.U
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, STATE_IDLE )
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, STATE_IDLE )
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val crcUnit = Module(new crc32_8)
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val crcOut = crcUnit.io.crc
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val crcUnit = Module(new crc32_8)
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val crcCmp = Reg(UInt(32.W))
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val crcOut = crcUnit.io.crc
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val crcCmp = Reg(UInt(32.W))
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = RegInit(0.U(12.W))
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = RegInit(0.U(12.W))
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val syncSerDat: Bool
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val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
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val syncSerDat: Bool
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val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
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val shiftData = Dualb4b5Decoder(checkSFD(9,0))
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val shiftData = Dualb4b5Decoder(checkSFD(9,0))
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val payloadLen = Reg(UInt(12.W))
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when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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val payloadLen = Reg(UInt(12.W))
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payloadLen := Cat( shiftData, 0.U(4.W) )
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when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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payloadLen := Cat( shiftData, 0.U(4.W) )
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payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
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} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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}
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payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
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}
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stateNext :=
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Mux1H(Seq(
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stateNext :=
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(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE
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Mux1H(Seq(
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(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
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(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE
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(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
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(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
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(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC
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(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
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))
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(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC
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))
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
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bitCnt := 0.U
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
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} .otherwise{
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bitCnt := 0.U
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when( bitCnt === 9.U ){
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} .otherwise{
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bitCnt := 0.U
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when( bitCnt === 9.U ){
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} .otherwise{
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bitCnt := 0.U
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bitCnt := bitCnt + 1.U
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} .otherwise{
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}
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bitCnt := bitCnt + 1.U
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}
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}
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}
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
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byteCnt := 0.U
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
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} .elsewhen( bitCnt === 9.U ){
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byteCnt := 0.U
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when( stateCurr === STATE_HEADER ){
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} .elsewhen( bitCnt === 9.U ){
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byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
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when( stateCurr === STATE_HEADER ){
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assert( byteCnt <= (HeaderByte-1).U )
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byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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assert( byteCnt <= (HeaderByte-1).U )
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byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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assert( byteCnt <= ( payloadLen-1.U ) )
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byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
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} .elsewhen( stateCurr === STATE_CRC ){
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assert( byteCnt <= ( payloadLen-1.U ) )
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byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U )
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} .elsewhen( stateCurr === STATE_CRC ){
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assert( byteCnt <= 3.U )
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byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U )
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}
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assert( byteCnt <= 3.U )
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}
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}
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}
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val axis_valid = RegInit(false.B)
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val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
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val axis_valid = RegInit(false.B)
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val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 9.U )
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val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
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val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 9.U )
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val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 9.U )
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val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 9.U )
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io.axis.valid := axis_valid
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io.axis.bits.tdata := axis_tdata
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io.axis.valid := axis_valid
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io.axis.bits.tuser := axis_tuser
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io.axis.bits.tdata := axis_tdata
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io.axis.bits.tlast := axis_tlast
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io.axis.bits.tuser := axis_tuser
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io.axis.bits.tlast := axis_tlast
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when( io.axis.fire ){
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axis_valid := false.B
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when( io.axis.fire ){
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} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
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axis_valid := false.B
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axis_valid := true.B
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} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
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}
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axis_valid := true.B
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}
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when( stateCurr === STATE_CRC & bitCnt === 9.U ){
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crcCmp := Cat( shiftData, crcCmp(31,8) )
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when( stateCurr === STATE_CRC & bitCnt === 9.U ){
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}
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crcCmp := Cat( shiftData, crcCmp(31,8) )
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}
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crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U )
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crcUnit.io.dataIn := shiftData
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crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U )
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crcUnit.io.dataIn := shiftData
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crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle
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crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle
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}
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}
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class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
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class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
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@@ -1,109 +1,109 @@
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package BACK
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package BACK
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import chisel3._
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import chisel3._
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import chisel3.util._
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import chisel3.util._
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class AXIS_Bundle(dw: Int) extends Bundle{
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class AXIS_Bundle(dw: Int) extends Bundle{
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val tdata = UInt(dw.W)
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val tdata = UInt(dw.W)
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val tlast = Bool()
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val tlast = Bool()
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val tuser = Bool()
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val tuser = Bool()
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}
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}
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//work in 100MHZ
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//work in 100MHZ
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class CDROutIO extends Bundle{
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class CDROutIO extends Bundle{
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val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
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val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
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val serDat = Output(Bool())
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val serDat = Output(Bool())
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}
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}
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class CDROut extends Module{
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class CDROut extends Module{
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val io: CDROutIO = IO(new CDROutIO)
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val io: CDROutIO = IO(new CDROutIO)
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val crcUnit = Module(new crc32_8)
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val crcUnit = Module(new crc32_8)
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def STATE_IDLE = 0.U
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def STATE_IDLE = 0.U
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def STATE_PREAMBLE = 1.U
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def STATE_PREAMBLE = 1.U
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def STATE_PAYLOAD = 2.U
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def STATE_PAYLOAD = 2.U
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def STATE_FCS = 3.U
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def STATE_FCS = 3.U
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val ETH_PRE = "h55".U
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val ETH_PRE = "h55".U
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val ETH_SFD = "hD5".U
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val ETH_SFD = "hD5".U
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val stateNext = Wire(UInt(2.W))
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, 0.U )
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val stateCurr = RegNext( stateNext, 0.U )
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||||||
val bitCnt = Reg(UInt(4.W))
|
val bitCnt = Reg(UInt(4.W))
|
||||||
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
|
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
|
||||||
|
|
||||||
val crcOut = crcUnit.io.crc
|
val crcOut = crcUnit.io.crc
|
||||||
val reset_crc = stateCurr === STATE_IDLE
|
val reset_crc = stateCurr === STATE_IDLE
|
||||||
crcUnit.reset := reset.asBool | reset_crc
|
crcUnit.reset := reset.asBool | reset_crc
|
||||||
|
|
||||||
crcUnit.io.dataIn := io.axis.bits.tdata
|
crcUnit.io.dataIn := io.axis.bits.tdata
|
||||||
crcUnit.io.isEnable := io.axis.fire
|
crcUnit.io.isEnable := io.axis.fire
|
||||||
|
|
||||||
val shiftData = RegInit(0.U(10.W))
|
val shiftData = RegInit(0.U(10.W))
|
||||||
|
|
||||||
stateNext := Mux1H(Seq(
|
stateNext := Mux1H(Seq(
|
||||||
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
|
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
|
||||||
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
|
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
|
||||||
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
|
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
|
||||||
(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
|
(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
|
||||||
))
|
))
|
||||||
|
|
||||||
io.serDat := shiftData.extract(9)
|
io.serDat := shiftData.extract(9)
|
||||||
io.axis.ready :=
|
io.axis.ready :=
|
||||||
bitCnt === 9.U & (
|
bitCnt === 9.U & (
|
||||||
(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
|
(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
|
||||||
(stateCurr === STATE_PAYLOAD)
|
(stateCurr === STATE_PAYLOAD)
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
|
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
|
||||||
shiftData := Dualb4b5Encoder(ETH_PRE)
|
shiftData := Dualb4b5Encoder(ETH_PRE)
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
when( bitCnt =/= 9.U ){
|
when( bitCnt =/= 9.U ){
|
||||||
shiftData := shiftData << 1
|
shiftData := shiftData << 1
|
||||||
} .otherwise{ //bitCnt === 9.U
|
} .otherwise{ //bitCnt === 9.U
|
||||||
when( stateCurr === STATE_PREAMBLE ){
|
when( stateCurr === STATE_PREAMBLE ){
|
||||||
shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
|
shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
|
||||||
( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
|
( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
|
||||||
( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
|
( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
|
||||||
))
|
))
|
||||||
} .elsewhen( stateCurr === STATE_PAYLOAD ){
|
} .elsewhen( stateCurr === STATE_PAYLOAD ){
|
||||||
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
|
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
|
||||||
} .elsewhen( stateCurr === STATE_FCS ){
|
} .elsewhen( stateCurr === STATE_FCS ){
|
||||||
shiftData := Mux1H(Seq(
|
shiftData := Mux1H(Seq(
|
||||||
( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
|
( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
|
||||||
( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
|
( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
|
||||||
( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
|
( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
|
||||||
( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
|
( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
|
||||||
))
|
))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
when( stateCurr === STATE_IDLE ){ //PRE
|
when( stateCurr === STATE_IDLE ){ //PRE
|
||||||
bitCnt := 0.U
|
bitCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
when( bitCnt === 9.U ){
|
when( bitCnt === 9.U ){
|
||||||
bitCnt := 0.U
|
bitCnt := 0.U
|
||||||
} .otherwise{
|
} .otherwise{
|
||||||
bitCnt := bitCnt + 1.U
|
bitCnt := bitCnt + 1.U
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
|
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
|
||||||
byteCnt := 0.U
|
byteCnt := 0.U
|
||||||
} .elsewhen( bitCnt === 9.U ){
|
} .elsewhen( bitCnt === 9.U ){
|
||||||
byteCnt := byteCnt + 1.U
|
byteCnt := byteCnt + 1.U
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -1,268 +1,295 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
import org.chipsalliance.cde.config._
|
import org.chipsalliance.cde.config._
|
||||||
import freechips.rocketchip.diplomacy._
|
import freechips.rocketchip.diplomacy._
|
||||||
import freechips.rocketchip.tilelink._
|
import freechips.rocketchip.tilelink._
|
||||||
|
|
||||||
|
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
|
||||||
abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
|
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
|
||||||
class TLCDRIO extends Bundle{
|
|
||||||
val overCLK = Input(Bool())
|
case object BackParamsKey extends Field[BackSetting]
|
||||||
val dDatIn = Input(Bool())
|
|
||||||
val dDatOut = Output(Bool())
|
case class BackSetting(
|
||||||
val uDatIn = Input(Bool())
|
){
|
||||||
val uDatOut = Output(Bool())
|
|
||||||
|
}
|
||||||
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
|
|
||||||
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
|
trait HasBackParameters {
|
||||||
|
implicit val p: Parameters
|
||||||
val interrupt = Output(Vec(4, Bool()))
|
|
||||||
}
|
val backSetting = p(BackParamsKey)
|
||||||
|
}
|
||||||
val io: TLCDRIO = IO(new TLCDRIO)
|
|
||||||
|
|
||||||
val dirSel = RegInit(false.B)
|
|
||||||
|
class BackCfg extends Config((_, _, _) => {
|
||||||
val CDRIn = Module(new CDRIn)
|
case BackParamsKey => BackSetting()
|
||||||
CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn )
|
})
|
||||||
CDRIn.io.overCLK := io.overCLK
|
|
||||||
|
|
||||||
val CDROut = Module(new CDROut)
|
|
||||||
io.dDatOut := ~dirSel & CDROut.io.serDat
|
|
||||||
io.uDatOut := dirSel & CDROut.io.serDat
|
|
||||||
|
|
||||||
|
abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
|
||||||
|
class TLCDRIO extends Bundle{
|
||||||
val txFifo = Module(new Queue(UInt(32.W), 16))
|
val overCLK = Input(Bool())
|
||||||
val rxFifo = Module(new Queue(UInt(32.W), 16))
|
val dDatIn = Input(Bool())
|
||||||
|
val dDatOut = Output(Bool())
|
||||||
|
val uDatIn = Input(Bool())
|
||||||
// val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
|
val uDatOut = Output(Bool())
|
||||||
val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
|
||||||
|
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
|
||||||
}
|
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
|
||||||
|
|
||||||
|
val interrupt = Output(Vec(4, Bool()))
|
||||||
trait TL2CDRTx{ this: TL2CDRBase =>
|
}
|
||||||
|
|
||||||
// val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U )
|
val io: TLCDRIO = IO(new TLCDRIO)
|
||||||
// val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
|
|
||||||
// val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
|
val dirSel = RegInit(false.B)
|
||||||
val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
|
|
||||||
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
val CDRIn = Module(new CDRIn)
|
||||||
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn )
|
||||||
|
CDRIn.io.overCLK := io.overCLK
|
||||||
|
|
||||||
val txLen = RegInit(0.U(12.W))
|
val CDROut = Module(new CDROut)
|
||||||
val isTxBusy = RegInit(false.B)
|
io.dDatOut := ~dirSel & CDROut.io.serDat
|
||||||
val isTxFull = ~txFifo.io.enq.ready
|
io.uDatOut := dirSel & CDROut.io.serDat
|
||||||
|
|
||||||
|
|
||||||
val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
|
|
||||||
println("Warning, TxEnd no confident\n")
|
val txFifo = Module(new Queue(UInt(32.W), 16))
|
||||||
val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull
|
val rxFifo = Module(new Queue(UInt(32.W), 16))
|
||||||
val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast
|
|
||||||
|
|
||||||
val txCnt = Reg(UInt(2.W))
|
// val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
|
||||||
|
val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||||
val txData = Reg(UInt(32.W))
|
|
||||||
|
}
|
||||||
when( txFifo.io.deq.fire ){ //txCnt === 3.U
|
|
||||||
txData := txFifo.io.deq.bits
|
|
||||||
when( isTxBusy ){
|
trait TL2CDRTx{ this: TL2CDRBase =>
|
||||||
assert(CDROut.io.axis.fire)
|
|
||||||
}
|
// val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U )
|
||||||
|
// val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
|
||||||
} .elsewhen( CDROut.io.axis.fire ){
|
// val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
|
||||||
txData := txData << 8
|
val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
|
||||||
}
|
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||||
|
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||||
txFifo.io.deq.ready :=
|
|
||||||
Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
|
|
||||||
|
val txLen = RegInit(0.U(12.W))
|
||||||
txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
|
val isTxBusy = RegInit(false.B)
|
||||||
CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
|
val isTxFull = ~txFifo.io.enq.ready
|
||||||
|
|
||||||
CDROut.io.axis.bits.tdata := txData.head(8)
|
|
||||||
|
val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
|
||||||
// PriorityMux(Seq(
|
println("Warning, TxEnd no confident\n")
|
||||||
// (txCnt === 0.U) -> txData(31, 24),
|
val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull
|
||||||
// (txCnt === 1.U) -> txData(23, 16),
|
val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast
|
||||||
// (txCnt === 2.U) -> txData(15, 8),
|
|
||||||
// (txCnt === 3.U) -> txData( 7, 0),
|
val txCnt = Reg(UInt(2.W))
|
||||||
// ))
|
|
||||||
|
val txData = Reg(UInt(32.W))
|
||||||
CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
|
|
||||||
CDROut.io.axis.bits.tuser := false.B
|
when( txFifo.io.deq.fire ){ //txCnt === 3.U
|
||||||
CDROut.io.axis.valid := isTxBusy
|
txData := txFifo.io.deq.bits
|
||||||
|
when( isTxBusy ){
|
||||||
|
assert(CDROut.io.axis.fire)
|
||||||
when( isTLWriteTxLen | isTLWriteSoftReset ){
|
}
|
||||||
isTxBusy := false.B
|
|
||||||
}.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){
|
} .elsewhen( CDROut.io.axis.fire ){
|
||||||
isTxBusy := true.B
|
txData := txData << 8
|
||||||
} .elsewhen( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast ){
|
}
|
||||||
isTxBusy := false.B
|
|
||||||
}
|
txFifo.io.deq.ready :=
|
||||||
|
Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
|
||||||
|
|
||||||
when( isTLWriteTxLen ){
|
txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
|
||||||
txCnt := 0.U
|
CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
|
||||||
} .elsewhen( CDROut.io.axis.fire ){
|
|
||||||
txCnt := txCnt + 1.U
|
CDROut.io.axis.bits.tdata := txData.head(8)
|
||||||
}
|
|
||||||
|
// PriorityMux(Seq(
|
||||||
|
// (txCnt === 0.U) -> txData(31, 24),
|
||||||
when( isTLWriteTxLen ){
|
// (txCnt === 1.U) -> txData(23, 16),
|
||||||
txLen := io.mem.wdata
|
// (txCnt === 2.U) -> txData(15, 8),
|
||||||
} .elsewhen( CDROut.io.axis.fire ){
|
// (txCnt === 3.U) -> txData( 7, 0),
|
||||||
txLen := txLen - 1.U
|
// ))
|
||||||
}
|
|
||||||
|
CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
|
||||||
txFifo.io.enq.bits := io.mem.wdata
|
CDROut.io.axis.bits.tuser := false.B
|
||||||
txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
|
CDROut.io.axis.valid := isTxBusy
|
||||||
|
|
||||||
|
|
||||||
}
|
when( isTLWriteTxLen | isTLWriteSoftReset ){
|
||||||
|
isTxBusy := false.B
|
||||||
|
}.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){
|
||||||
trait TL2CDRRx{ this: TL2CDRBase =>
|
isTxBusy := true.B
|
||||||
|
} .elsewhen( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast ){
|
||||||
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
|
isTxBusy := false.B
|
||||||
// val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
|
}
|
||||||
// val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
|
|
||||||
|
|
||||||
// val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
|
when( isTLWriteTxLen ){
|
||||||
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
|
txCnt := 0.U
|
||||||
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
|
} .elsewhen( CDROut.io.axis.fire ){
|
||||||
|
txCnt := txCnt + 1.U
|
||||||
|
}
|
||||||
val rxLen = RegInit(0.U(12.W))
|
|
||||||
val isRxValid = rxFifo.io.enq.fire
|
|
||||||
val isRxError = RegInit(false.B)
|
when( isTLWriteTxLen ){
|
||||||
val isAxisEnd = RegInit(false.B)
|
// txLen := io.mem.wdata
|
||||||
val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid
|
txLen := io.tla.bits.data
|
||||||
|
} .elsewhen( CDROut.io.axis.fire ){
|
||||||
val intRxError = ~RegNext(isRxError, false.B) & isRxError
|
txLen := txLen - 1.U
|
||||||
val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
|
}
|
||||||
val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd
|
|
||||||
|
txFifo.io.enq.bits := io.tla.bits.data
|
||||||
|
txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
|
||||||
val rxCnt = RegInit(0.U(2.W))
|
|
||||||
val rxData = Reg(UInt(24.W))
|
|
||||||
|
}
|
||||||
when( isTLWriteSoftReset ){
|
|
||||||
isAxisEnd := false.B
|
|
||||||
} .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
|
trait TL2CDRRx{ this: TL2CDRBase =>
|
||||||
isAxisEnd := true.B
|
|
||||||
}
|
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
|
||||||
|
// val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
|
||||||
|
// val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
|
||||||
when( isTLWriteSoftReset ){
|
|
||||||
rxCnt := 0.U
|
// val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
|
||||||
} .elsewhen( CDRIn.io.axis.fire ){
|
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
|
||||||
rxCnt := rxCnt + 1.U
|
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
|
||||||
|
|
||||||
rxData := Cat( rxData, CDRIn.io.axis.bits.tdata )
|
|
||||||
}
|
val rxLen = RegInit(0.U(12.W))
|
||||||
|
val isRxValid = rxFifo.io.enq.fire
|
||||||
when( isTLWriteSoftReset ){
|
val isRxError = RegInit(false.B)
|
||||||
rxLen := 0.U
|
val isAxisEnd = RegInit(false.B)
|
||||||
} .elsewhen( CDRIn.io.axis.fire ){
|
val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid
|
||||||
rxLen := rxLen + 1.U
|
|
||||||
}
|
val intRxError = ~RegNext(isRxError, false.B) & isRxError
|
||||||
|
val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
|
||||||
rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U
|
val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd
|
||||||
rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata )
|
|
||||||
|
|
||||||
assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
|
val rxCnt = RegInit(0.U(2.W))
|
||||||
|
val rxData = Reg(UInt(24.W))
|
||||||
CDRIn.io.axis.ready := true.B
|
|
||||||
|
when( isTLWriteSoftReset ){
|
||||||
rxFifo.reset := reset.asBool | isTLWriteSoftReset
|
isAxisEnd := false.B
|
||||||
CDRIn.reset := reset.asBool | isTLWriteSoftReset
|
} .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
|
||||||
|
isAxisEnd := true.B
|
||||||
rxFifo.io.deq.ready := isTLReadRxFifo
|
}
|
||||||
|
|
||||||
|
|
||||||
when( isTLWriteSoftReset ){
|
when( isTLWriteSoftReset ){
|
||||||
isRxError := false.B
|
rxCnt := 0.U
|
||||||
} .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){
|
} .elsewhen( CDRIn.io.axis.fire ){
|
||||||
isRxError := true.B
|
rxCnt := rxCnt + 1.U
|
||||||
printf("Warning, RxFifo Overflow!\n")
|
|
||||||
}
|
rxData := Cat( rxData, CDRIn.io.axis.bits.tdata )
|
||||||
|
}
|
||||||
|
|
||||||
|
when( isTLWriteSoftReset ){
|
||||||
}
|
rxLen := 0.U
|
||||||
|
} .elsewhen( CDRIn.io.axis.fire ){
|
||||||
class TL2CDR()(implicit p: Parameters) extends TL2CDRBase() with TL2CDRTx with TL2CDRRx{
|
rxLen := rxLen + 1.U
|
||||||
|
}
|
||||||
// val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
|
|
||||||
val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U
|
||||||
|
rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata )
|
||||||
val tlaInfo = Reg(new TLBundleA(edge.bundle))
|
|
||||||
val rdata = Reg(UInt(32.W))
|
assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
|
||||||
val tlAReady = RegInit(true.B)
|
|
||||||
val tlDValid = RegInit(false.B)
|
CDRIn.io.axis.ready := true.B
|
||||||
|
|
||||||
val isRead = tlaInfo.opcode === 4.U
|
rxFifo.reset := reset.asBool | isTLWriteSoftReset
|
||||||
|
CDRIn.reset := reset.asBool | isTLWriteSoftReset
|
||||||
when( isWriteTransDir ){
|
|
||||||
// dirSel := io.mem.wdata
|
rxFifo.io.deq.ready := isTLReadRxFifo
|
||||||
dirSel := io.tla.bits.data
|
|
||||||
}
|
|
||||||
|
when( isTLWriteSoftReset ){
|
||||||
// io.mem.ready :=
|
isRxError := false.B
|
||||||
// ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
|
} .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){
|
||||||
// ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
|
isRxError := true.B
|
||||||
|
printf("Warning, RxFifo Overflow!\n")
|
||||||
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
|
}
|
||||||
io.tld.valid := tlDValid
|
|
||||||
|
|
||||||
io.interrupt(0) := intTxEnd
|
|
||||||
io.interrupt(1) := intRxError
|
}
|
||||||
io.interrupt(2) := intRxStart
|
|
||||||
io.interrupt(3) := intRxEnd
|
class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) with TL2CDRTx with TL2CDRRx{
|
||||||
|
|
||||||
|
// val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
|
||||||
// io.mem.rdata :=
|
val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||||
// Mux1H(Seq(
|
|
||||||
// isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B),
|
val tlaInfo = Reg(new TLBundleA(edge.bundle))
|
||||||
// isTLReadRxLen -> rxLen,
|
val rdata = Reg(UInt(32.W))
|
||||||
// isTLReadRxFifo -> rxFifo.io.deq.bits
|
val tlAReady = RegInit(true.B)
|
||||||
// ))
|
val tlDValid = RegInit(false.B)
|
||||||
|
|
||||||
when( io.tla.fire ) {
|
val isRead = tlaInfo.opcode === 4.U
|
||||||
tlaInfo := io.tla.bits
|
|
||||||
}
|
when( isWriteTransDir ){
|
||||||
|
// dirSel := io.mem.wdata
|
||||||
when( io.tla.fire ){
|
dirSel := io.tla.bits.data
|
||||||
tlAReady := false.B
|
}
|
||||||
tlDValid := true.B
|
|
||||||
} .elsewhen( io.tld.fire ) {
|
// io.mem.ready :=
|
||||||
tlAReady := true.B
|
// ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
|
||||||
tlDValid := false.B
|
// ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
|
||||||
}
|
|
||||||
|
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
|
||||||
when(isRead) {
|
io.tld.valid := tlDValid
|
||||||
io.tld.bits := edge.AccessAck(tlaInfo, rdata)
|
|
||||||
} .otherwise {
|
io.interrupt(0) := intTxEnd
|
||||||
io.tld.bits := edge.AccessAck(tlaInfo)
|
io.interrupt(1) := intRxError
|
||||||
}
|
io.interrupt(2) := intRxStart
|
||||||
|
io.interrupt(3) := intRxEnd
|
||||||
when( isTLReadStatus){
|
|
||||||
rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError )
|
|
||||||
} .elsewhen(isTLReadRxLen ){
|
// io.mem.rdata :=
|
||||||
rdata := rxLen
|
// Mux1H(Seq(
|
||||||
} .elsewhen(isTLReadRxFifo ){
|
// isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B),
|
||||||
rdata := rxFifo.io.deq.bits
|
// isTLReadRxLen -> rxLen,
|
||||||
}
|
// isTLReadRxFifo -> rxFifo.io.deq.bits
|
||||||
|
// ))
|
||||||
|
|
||||||
}
|
when( io.tla.fire ) {
|
||||||
|
tlaInfo := io.tla.bits
|
||||||
|
}
|
||||||
|
|
||||||
|
when( io.tla.fire ){
|
||||||
|
tlAReady := false.B
|
||||||
|
tlDValid := true.B
|
||||||
|
} .elsewhen( io.tld.fire ) {
|
||||||
|
tlAReady := true.B
|
||||||
|
tlDValid := false.B
|
||||||
|
}
|
||||||
|
|
||||||
|
when(isRead) {
|
||||||
|
io.tld.bits := edge.AccessAck(tlaInfo, rdata)
|
||||||
|
} .otherwise {
|
||||||
|
io.tld.bits := edge.AccessAck(tlaInfo)
|
||||||
|
}
|
||||||
|
|
||||||
|
when( isTLReadStatus){
|
||||||
|
rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B )
|
||||||
|
} .elsewhen(isTLReadRxLen ){
|
||||||
|
rdata := rxLen
|
||||||
|
} .elsewhen(isTLReadRxFifo ){
|
||||||
|
rdata := rxFifo.io.deq.bits
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,65 +1,65 @@
|
|||||||
package BACK
|
package BACK
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
object b4b5Encoder{
|
object b4b5Encoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(enq === "b0000".U) -> "b11110".U(5.W),
|
(enq === "b0000".U) -> "b11110".U(5.W),
|
||||||
(enq === "b0001".U) -> "b01001".U(5.W),
|
(enq === "b0001".U) -> "b01001".U(5.W),
|
||||||
(enq === "b0010".U) -> "b10100".U(5.W),
|
(enq === "b0010".U) -> "b10100".U(5.W),
|
||||||
(enq === "b0011".U) -> "b10101".U(5.W),
|
(enq === "b0011".U) -> "b10101".U(5.W),
|
||||||
(enq === "b0100".U) -> "b01010".U(5.W),
|
(enq === "b0100".U) -> "b01010".U(5.W),
|
||||||
(enq === "b0101".U) -> "b01011".U(5.W),
|
(enq === "b0101".U) -> "b01011".U(5.W),
|
||||||
(enq === "b0110".U) -> "b01110".U(5.W),
|
(enq === "b0110".U) -> "b01110".U(5.W),
|
||||||
(enq === "b0111".U) -> "b01111".U(5.W),
|
(enq === "b0111".U) -> "b01111".U(5.W),
|
||||||
(enq === "b1000".U) -> "b10010".U(5.W),
|
(enq === "b1000".U) -> "b10010".U(5.W),
|
||||||
(enq === "b1001".U) -> "b10011".U(5.W),
|
(enq === "b1001".U) -> "b10011".U(5.W),
|
||||||
(enq === "b1010".U) -> "b10110".U(5.W),
|
(enq === "b1010".U) -> "b10110".U(5.W),
|
||||||
(enq === "b1011".U) -> "b10111".U(5.W),
|
(enq === "b1011".U) -> "b10111".U(5.W),
|
||||||
(enq === "b1100".U) -> "b11010".U(5.W),
|
(enq === "b1100".U) -> "b11010".U(5.W),
|
||||||
(enq === "b1101".U) -> "b11011".U(5.W),
|
(enq === "b1101".U) -> "b11011".U(5.W),
|
||||||
(enq === "b1110".U) -> "b11100".U(5.W),
|
(enq === "b1110".U) -> "b11100".U(5.W),
|
||||||
(enq === "b1111".U) -> "b11101".U(5.W),
|
(enq === "b1111".U) -> "b11101".U(5.W),
|
||||||
))
|
))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object b4b5Decoder{
|
object b4b5Decoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
Mux1H(Seq(
|
Mux1H(Seq(
|
||||||
(enq === "b11110".U) -> "b0000".U(4.W),
|
(enq === "b11110".U) -> "b0000".U(4.W),
|
||||||
(enq === "b01001".U) -> "b0001".U(4.W),
|
(enq === "b01001".U) -> "b0001".U(4.W),
|
||||||
(enq === "b10100".U) -> "b0010".U(4.W),
|
(enq === "b10100".U) -> "b0010".U(4.W),
|
||||||
(enq === "b10101".U) -> "b0011".U(4.W),
|
(enq === "b10101".U) -> "b0011".U(4.W),
|
||||||
(enq === "b01010".U) -> "b0100".U(4.W),
|
(enq === "b01010".U) -> "b0100".U(4.W),
|
||||||
(enq === "b01011".U) -> "b0101".U(4.W),
|
(enq === "b01011".U) -> "b0101".U(4.W),
|
||||||
(enq === "b01110".U) -> "b0110".U(4.W),
|
(enq === "b01110".U) -> "b0110".U(4.W),
|
||||||
(enq === "b01111".U) -> "b0111".U(4.W),
|
(enq === "b01111".U) -> "b0111".U(4.W),
|
||||||
(enq === "b10010".U) -> "b1000".U(4.W),
|
(enq === "b10010".U) -> "b1000".U(4.W),
|
||||||
(enq === "b10011".U) -> "b1001".U(4.W),
|
(enq === "b10011".U) -> "b1001".U(4.W),
|
||||||
(enq === "b10110".U) -> "b1010".U(4.W),
|
(enq === "b10110".U) -> "b1010".U(4.W),
|
||||||
(enq === "b10111".U) -> "b1011".U(4.W),
|
(enq === "b10111".U) -> "b1011".U(4.W),
|
||||||
(enq === "b11010".U) -> "b1100".U(4.W),
|
(enq === "b11010".U) -> "b1100".U(4.W),
|
||||||
(enq === "b11011".U) -> "b1101".U(4.W),
|
(enq === "b11011".U) -> "b1101".U(4.W),
|
||||||
(enq === "b11100".U) -> "b1110".U(4.W),
|
(enq === "b11100".U) -> "b1110".U(4.W),
|
||||||
(enq === "b11101".U) -> "b1111".U(4.W),
|
(enq === "b11101".U) -> "b1111".U(4.W),
|
||||||
))
|
))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object Dualb4b5Encoder{
|
object Dualb4b5Encoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
require( enq.width == 8 )
|
require( enq.getWidth == 8 )
|
||||||
Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) )
|
Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
object Dualb4b5Decoder{
|
object Dualb4b5Decoder{
|
||||||
def apply( enq: UInt ): UInt = {
|
def apply( enq: UInt ): UInt = {
|
||||||
require( enq.width == 10 )
|
require( enq.getWidth == 10 )
|
||||||
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(5,0)) )
|
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(5,0)) )
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -11,27 +11,7 @@ import sifive.blocks.devices.uart._
|
|||||||
import sifive.blocks.devices.gpio._
|
import sifive.blocks.devices.gpio._
|
||||||
|
|
||||||
|
|
||||||
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
|
|
||||||
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
|
|
||||||
|
|
||||||
case object BackParamsKey extends Field[BackSetting]
|
|
||||||
|
|
||||||
case class BackSetting(
|
|
||||||
){
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
trait HasBackParameters {
|
|
||||||
implicit val p: Parameters
|
|
||||||
|
|
||||||
val backSetting = p(BackParamsKey)
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class BackCfg extends Config((_, _, _) => {
|
|
||||||
case BackParamsKey => BackSetting()
|
|
||||||
})
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user