From 134440812b4144de5134bf33eef295b5965d2f8d Mon Sep 17 00:00:00 2001 From: "Ruige Lee (WSL)" <295054118@whut.edu.cn> Date: Thu, 9 Jan 2025 19:10:07 +0800 Subject: [PATCH] compile without tl2cdr --- src/main/scala/backBoard/ebus/CDRIn.scala | 389 ++++++------ src/main/scala/backBoard/ebus/CDROut.scala | 218 +++---- src/main/scala/backBoard/ebus/TL2CDR.scala | 563 +++++++++--------- src/main/scala/backBoard/ebus/b4b5.scala | 130 ++-- .../scala/backBoard/pico/BackSystem.scala | 20 - 5 files changed, 664 insertions(+), 656 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 2c501e2..db5b91b 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -1,194 +1,195 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -//work in 100MHZ -class CDRInIO extends Bundle{ - val axis = Decoupled(new AXIS_Bundle(8)) - val serDat = Input(Bool()) - val overCLK = Input(Bool()) -} - - -abstract class CDRInBase extends Module{ - def sampleRate: Int = 4 - require( sampleRate == 4 ) - - val io: CDRInIO = IO(new CDRInIO) - - -} - -trait CDRInOverSample{ this: CDRInBase => - val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } - - - - // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) } - // val arbSel = Reg(UInt( log2Ceil(sampleRate).W )) - // val isArbLock = RegInit(false.B) - - // for( i <- 0 until sampleRate ){ - // arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) ) - // when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){ - // isArbLock := true.B - // arbSel := i.U - // } - // } - - // when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){ - // isArbLock := false.B - // } - - // val syncSerDat = - // Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } ) - - val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)); arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) ) } - val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } - when( sampleReg(0) ^ sampleReg(1) ){ - arbLock := arbCnt - } - - val asyncSerDat = Mux1H(Seq( - (arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3), - (arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0), - (arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1), - (arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2), - - (arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2), - (arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3), - (arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0), - (arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1), - - (arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1), - (arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2), - (arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3), - (arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0), - - (arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0), - (arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1), - (arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2), - (arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3), - )) - - - val syncSerDat = ShiftRegister( asyncSerDat, 2 ) - - - - -} - - -trait CDRInAxis{ this: CDRInBase => - - def HeaderByte: Int = 8 - - val ETH_PRE = "h55".U(8.W) - val ETH_SFD = "hD5".U(8.W) - - val STATE_IDLE = 0.U - val STATE_HEADER = 1.U - val STATE_PAYLOAD = 2.U - val STATE_CRC = 3.U - - - - - val stateNext = Wire(UInt(2.W)) - val stateCurr = RegNext( stateNext, STATE_IDLE ) - - val crcUnit = Module(new crc32_8) - val crcOut = crcUnit.io.crc - val crcCmp = Reg(UInt(32.W)) - - val bitCnt = Reg(UInt(4.W)) - val byteCnt = RegInit(0.U(12.W)) - - val syncSerDat: Bool - val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) - - val shiftData = Dualb4b5Decoder(checkSFD(9,0)) - - val payloadLen = Reg(UInt(12.W)) - when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ - payloadLen := Cat( shiftData, 0.U(4.W) ) - } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ - payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ) - } - - stateNext := - Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE - (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD - (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC - )) - - - - - - when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align - bitCnt := 0.U - } .otherwise{ - when( bitCnt === 9.U ){ - bitCnt := 0.U - } .otherwise{ - bitCnt := bitCnt + 1.U - } - } - - when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align - byteCnt := 0.U - } .elsewhen( bitCnt === 9.U ){ - when( stateCurr === STATE_HEADER ){ - byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) - assert( byteCnt <= (HeaderByte-1).U ) - } .elsewhen( stateCurr === STATE_PAYLOAD ){ - byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U ) - assert( byteCnt <= ( payloadLen-1.U ) ) - } .elsewhen( stateCurr === STATE_CRC ){ - byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U ) - assert( byteCnt <= 3.U ) - } - } - - - - - - val axis_valid = RegInit(false.B) - val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) - val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 9.U ) - val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 9.U ) - - io.axis.valid := axis_valid - io.axis.bits.tdata := axis_tdata - io.axis.bits.tuser := axis_tuser - io.axis.bits.tlast := axis_tlast - - - when( io.axis.fire ){ - axis_valid := false.B - } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){ - axis_valid := true.B - } - - when( stateCurr === STATE_CRC & bitCnt === 9.U ){ - crcCmp := Cat( shiftData, crcCmp(31,8) ) - } - - - crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U ) - crcUnit.io.dataIn := shiftData - - crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle - -} - - -class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis - +package BACK + +import chisel3._ +import chisel3.util._ + + +//work in 100MHZ +class CDRInIO extends Bundle{ + val axis = Decoupled(new AXIS_Bundle(8)) + val serDat = Input(Bool()) + val overCLK = Input(Bool()) +} + + +abstract class CDRInBase extends Module{ + def sampleRate: Int = 4 + require( sampleRate == 4 ) + + val io: CDRInIO = IO(new CDRInIO) + + +} + +trait CDRInOverSample{ this: CDRInBase => + val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } + + + + // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) } + // val arbSel = Reg(UInt( log2Ceil(sampleRate).W )) + // val isArbLock = RegInit(false.B) + + // for( i <- 0 until sampleRate ){ + // arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) ) + // when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){ + // isArbLock := true.B + // arbSel := i.U + // } + // } + + // when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){ + // isArbLock := false.B + // } + + // val syncSerDat = + // Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } ) + + val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) } + arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) ) + val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } + when( sampleReg(0) ^ sampleReg(1) ){ + arbLock := arbCnt + } + + val asyncSerDat = Mux1H(Seq( + (arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3), + (arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0), + (arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1), + (arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2), + + (arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2), + (arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3), + (arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0), + (arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1), + + (arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1), + (arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2), + (arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3), + (arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0), + + (arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0), + (arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1), + (arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2), + (arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3), + )) + + + val syncSerDat = ShiftRegister( asyncSerDat, 2 ) + + + + +} + + +trait CDRInAxis{ this: CDRInBase => + + def HeaderByte: Int = 8 + + val ETH_PRE = "h55".U(8.W) + val ETH_SFD = "hD5".U(8.W) + + val STATE_IDLE = 0.U + val STATE_HEADER = 1.U + val STATE_PAYLOAD = 2.U + val STATE_CRC = 3.U + + + + + val stateNext = Wire(UInt(2.W)) + val stateCurr = RegNext( stateNext, STATE_IDLE ) + + val crcUnit = Module(new crc32_8) + val crcOut = crcUnit.io.crc + val crcCmp = Reg(UInt(32.W)) + + val bitCnt = Reg(UInt(4.W)) + val byteCnt = RegInit(0.U(12.W)) + + val syncSerDat: Bool + val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) + + val shiftData = Dualb4b5Decoder(checkSFD(9,0)) + + val payloadLen = Reg(UInt(12.W)) + when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ + payloadLen := Cat( shiftData, 0.U(4.W) ) + } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ + payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ) + } + + stateNext := + Mux1H(Seq( + (stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE + (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), + (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD + (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC + )) + + + + + + when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align + bitCnt := 0.U + } .otherwise{ + when( bitCnt === 9.U ){ + bitCnt := 0.U + } .otherwise{ + bitCnt := bitCnt + 1.U + } + } + + when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align + byteCnt := 0.U + } .elsewhen( bitCnt === 9.U ){ + when( stateCurr === STATE_HEADER ){ + byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) + assert( byteCnt <= (HeaderByte-1).U ) + } .elsewhen( stateCurr === STATE_PAYLOAD ){ + byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U ) + assert( byteCnt <= ( payloadLen-1.U ) ) + } .elsewhen( stateCurr === STATE_CRC ){ + byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U ) + assert( byteCnt <= 3.U ) + } + } + + + + + + val axis_valid = RegInit(false.B) + val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) + val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 9.U ) + val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 9.U ) + + io.axis.valid := axis_valid + io.axis.bits.tdata := axis_tdata + io.axis.bits.tuser := axis_tuser + io.axis.bits.tlast := axis_tlast + + + when( io.axis.fire ){ + axis_valid := false.B + } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){ + axis_valid := true.B + } + + when( stateCurr === STATE_CRC & bitCnt === 9.U ){ + crcCmp := Cat( shiftData, crcCmp(31,8) ) + } + + + crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U ) + crcUnit.io.dataIn := shiftData + + crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle + +} + + +class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis + diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index 9768c4a..bf87a7f 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -1,109 +1,109 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -class AXIS_Bundle(dw: Int) extends Bundle{ - val tdata = UInt(dw.W) - val tlast = Bool() - val tuser = Bool() -} - -//work in 100MHZ -class CDROutIO extends Bundle{ - val axis = Flipped(Decoupled(new AXIS_Bundle(8))) - val serDat = Output(Bool()) -} - - - -class CDROut extends Module{ - val io: CDROutIO = IO(new CDROutIO) - - val crcUnit = Module(new crc32_8) - - def STATE_IDLE = 0.U - def STATE_PREAMBLE = 1.U - def STATE_PAYLOAD = 2.U - def STATE_FCS = 3.U - - - val ETH_PRE = "h55".U - val ETH_SFD = "hD5".U - - val stateNext = Wire(UInt(2.W)) - val stateCurr = RegNext( stateNext, 0.U ) - - - val bitCnt = Reg(UInt(4.W)) - val byteCnt = Reg(UInt(3.W)) //payload dont need to count - - val crcOut = crcUnit.io.crc - val reset_crc = stateCurr === STATE_IDLE - crcUnit.reset := reset.asBool | reset_crc - - crcUnit.io.dataIn := io.axis.bits.tdata - crcUnit.io.isEnable := io.axis.fire - - val shiftData = RegInit(0.U(10.W)) - - stateNext := Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), - (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )), - (stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ), - (stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )), - )) - - io.serDat := shiftData.extract(9) - io.axis.ready := - bitCnt === 9.U & ( - (stateCurr === STATE_PREAMBLE & byteCnt === 7.U) | - (stateCurr === STATE_PAYLOAD) - ) - - - - when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE - shiftData := Dualb4b5Encoder(ETH_PRE) - } .otherwise{ - when( bitCnt =/= 9.U ){ - shiftData := shiftData << 1 - } .otherwise{ //bitCnt === 9.U - when( stateCurr === STATE_PREAMBLE ){ - shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array( - ( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD), - ( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata), - )) - } .elsewhen( stateCurr === STATE_PAYLOAD ){ - shiftData := Dualb4b5Encoder(io.axis.bits.tdata) - } .elsewhen( stateCurr === STATE_FCS ){ - shiftData := Mux1H(Seq( - ( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ), - ( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ), - ( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)), - ( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)), - )) - } - } - } - - - when( stateCurr === STATE_IDLE ){ //PRE - bitCnt := 0.U - } .otherwise{ - when( bitCnt === 9.U ){ - bitCnt := 0.U - } .otherwise{ - bitCnt := bitCnt + 1.U - } - } - - when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ - byteCnt := 0.U - } .elsewhen( bitCnt === 9.U ){ - byteCnt := byteCnt + 1.U - } - - -} - +package BACK + +import chisel3._ +import chisel3.util._ + +class AXIS_Bundle(dw: Int) extends Bundle{ + val tdata = UInt(dw.W) + val tlast = Bool() + val tuser = Bool() +} + +//work in 100MHZ +class CDROutIO extends Bundle{ + val axis = Flipped(Decoupled(new AXIS_Bundle(8))) + val serDat = Output(Bool()) +} + + + +class CDROut extends Module{ + val io: CDROutIO = IO(new CDROutIO) + + val crcUnit = Module(new crc32_8) + + def STATE_IDLE = 0.U + def STATE_PREAMBLE = 1.U + def STATE_PAYLOAD = 2.U + def STATE_FCS = 3.U + + + val ETH_PRE = "h55".U + val ETH_SFD = "hD5".U + + val stateNext = Wire(UInt(2.W)) + val stateCurr = RegNext( stateNext, 0.U ) + + + val bitCnt = Reg(UInt(4.W)) + val byteCnt = Reg(UInt(3.W)) //payload dont need to count + + val crcOut = crcUnit.io.crc + val reset_crc = stateCurr === STATE_IDLE + crcUnit.reset := reset.asBool | reset_crc + + crcUnit.io.dataIn := io.axis.bits.tdata + crcUnit.io.isEnable := io.axis.fire + + val shiftData = RegInit(0.U(10.W)) + + stateNext := Mux1H(Seq( + (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), + (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )), + (stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ), + (stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )), + )) + + io.serDat := shiftData.extract(9) + io.axis.ready := + bitCnt === 9.U & ( + (stateCurr === STATE_PREAMBLE & byteCnt === 7.U) | + (stateCurr === STATE_PAYLOAD) + ) + + + + when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE + shiftData := Dualb4b5Encoder(ETH_PRE) + } .otherwise{ + when( bitCnt =/= 9.U ){ + shiftData := shiftData << 1 + } .otherwise{ //bitCnt === 9.U + when( stateCurr === STATE_PREAMBLE ){ + shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array( + ( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD), + ( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata), + )) + } .elsewhen( stateCurr === STATE_PAYLOAD ){ + shiftData := Dualb4b5Encoder(io.axis.bits.tdata) + } .elsewhen( stateCurr === STATE_FCS ){ + shiftData := Mux1H(Seq( + ( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ), + ( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ), + ( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)), + ( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)), + )) + } + } + } + + + when( stateCurr === STATE_IDLE ){ //PRE + bitCnt := 0.U + } .otherwise{ + when( bitCnt === 9.U ){ + bitCnt := 0.U + } .otherwise{ + bitCnt := bitCnt + 1.U + } + } + + when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ + byteCnt := 0.U + } .elsewhen( bitCnt === 9.U ){ + byteCnt := byteCnt + 1.U + } + + +} + diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala index 176a974..16aac2a 100644 --- a/src/main/scala/backBoard/ebus/TL2CDR.scala +++ b/src/main/scala/backBoard/ebus/TL2CDR.scala @@ -1,268 +1,295 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - - -abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule { - class TLCDRIO extends Bundle{ - val overCLK = Input(Bool()) - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - - val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle))) - val tld = new DecoupledIO(new TLBundleD(edge.bundle)) - - val interrupt = Output(Vec(4, Bool())) - } - - val io: TLCDRIO = IO(new TLCDRIO) - - val dirSel = RegInit(false.B) - - val CDRIn = Module(new CDRIn) - CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn ) - CDRIn.io.overCLK := io.overCLK - - val CDROut = Module(new CDROut) - io.dDatOut := ~dirSel & CDROut.io.serDat - io.uDatOut := dirSel & CDROut.io.serDat - - - - val txFifo = Module(new Queue(UInt(32.W), 16)) - val rxFifo = Module(new Queue(UInt(32.W), 16)) - - - // val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) ) - val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - -} - - -trait TL2CDRTx{ this: TL2CDRBase => - - // val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U ) - // val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U ) - // val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U ) - val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) - val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - - - val txLen = RegInit(0.U(12.W)) - val isTxBusy = RegInit(false.B) - val isTxFull = ~txFifo.io.enq.ready - - - val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B) - println("Warning, TxEnd no confident\n") - val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull - val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast - - val txCnt = Reg(UInt(2.W)) - - val txData = Reg(UInt(32.W)) - - when( txFifo.io.deq.fire ){ //txCnt === 3.U - txData := txFifo.io.deq.bits - when( isTxBusy ){ - assert(CDROut.io.axis.fire) - } - - } .elsewhen( CDROut.io.axis.fire ){ - txData := txData << 8 - } - - txFifo.io.deq.ready := - Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B ) - - txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset - CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset - - CDROut.io.axis.bits.tdata := txData.head(8) - - // PriorityMux(Seq( - // (txCnt === 0.U) -> txData(31, 24), - // (txCnt === 1.U) -> txData(23, 16), - // (txCnt === 2.U) -> txData(15, 8), - // (txCnt === 3.U) -> txData( 7, 0), - // )) - - CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U - CDROut.io.axis.bits.tuser := false.B - CDROut.io.axis.valid := isTxBusy - - - when( isTLWriteTxLen | isTLWriteSoftReset ){ - isTxBusy := false.B - }.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){ - isTxBusy := true.B - } .elsewhen( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast ){ - isTxBusy := false.B - } - - - when( isTLWriteTxLen ){ - txCnt := 0.U - } .elsewhen( CDROut.io.axis.fire ){ - txCnt := txCnt + 1.U - } - - - when( isTLWriteTxLen ){ - txLen := io.mem.wdata - } .elsewhen( CDROut.io.axis.fire ){ - txLen := txLen - 1.U - } - - txFifo.io.enq.bits := io.mem.wdata - txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U - - -} - - -trait TL2CDRRx{ this: TL2CDRBase => - - // val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U ) - // val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U ) - // val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U ) - - // val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) - val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) - val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) - - - val rxLen = RegInit(0.U(12.W)) - val isRxValid = rxFifo.io.enq.fire - val isRxError = RegInit(false.B) - val isAxisEnd = RegInit(false.B) - val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid - - val intRxError = ~RegNext(isRxError, false.B) & isRxError - val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire - val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd - - - val rxCnt = RegInit(0.U(2.W)) - val rxData = Reg(UInt(24.W)) - - when( isTLWriteSoftReset ){ - isAxisEnd := false.B - } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){ - isAxisEnd := true.B - } - - - when( isTLWriteSoftReset ){ - rxCnt := 0.U - } .elsewhen( CDRIn.io.axis.fire ){ - rxCnt := rxCnt + 1.U - - rxData := Cat( rxData, CDRIn.io.axis.bits.tdata ) - } - - when( isTLWriteSoftReset ){ - rxLen := 0.U - } .elsewhen( CDRIn.io.axis.fire ){ - rxLen := rxLen + 1.U - } - - rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U - rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ) - - assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) - - CDRIn.io.axis.ready := true.B - - rxFifo.reset := reset.asBool | isTLWriteSoftReset - CDRIn.reset := reset.asBool | isTLWriteSoftReset - - rxFifo.io.deq.ready := isTLReadRxFifo - - - when( isTLWriteSoftReset ){ - isRxError := false.B - } .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){ - isRxError := true.B - printf("Warning, RxFifo Overflow!\n") - } - - - -} - -class TL2CDR()(implicit p: Parameters) extends TL2CDRBase() with TL2CDRTx with TL2CDRRx{ - - // val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U - val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - - val tlaInfo = Reg(new TLBundleA(edge.bundle)) - val rdata = Reg(UInt(32.W)) - val tlAReady = RegInit(true.B) - val tlDValid = RegInit(false.B) - - val isRead = tlaInfo.opcode === 4.U - - when( isWriteTransDir ){ - // dirSel := io.mem.wdata - dirSel := io.tla.bits.data - } - - // io.mem.ready := - // ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | - // ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) ) - - io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) ) - io.tld.valid := tlDValid - - io.interrupt(0) := intTxEnd - io.interrupt(1) := intRxError - io.interrupt(2) := intRxStart - io.interrupt(3) := intRxEnd - - - // io.mem.rdata := - // Mux1H(Seq( - // isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B), - // isTLReadRxLen -> rxLen, - // isTLReadRxFifo -> rxFifo.io.deq.bits - // )) - - when( io.tla.fire ) { - tlaInfo := io.tla.bits - } - - when( io.tla.fire ){ - tlAReady := false.B - tlDValid := true.B - } .elsewhen( io.tld.fire ) { - tlAReady := true.B - tlDValid := false.B - } - - when(isRead) { - io.tld.bits := edge.AccessAck(tlaInfo, rdata) - } .otherwise { - io.tld.bits := edge.AccessAck(tlaInfo) - } - - when( isTLReadStatus){ - rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError ) - } .elsewhen(isTLReadRxLen ){ - rdata := rxLen - } .elsewhen(isTLReadRxFifo ){ - rdata := rxFifo.io.deq.bits - } - - -} - - +package BACK + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record } +abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters + +case object BackParamsKey extends Field[BackSetting] + +case class BackSetting( +){ + +} + +trait HasBackParameters { + implicit val p: Parameters + + val backSetting = p(BackParamsKey) +} + + + +class BackCfg extends Config((_, _, _) => { + case BackParamsKey => BackSetting() +}) + + + + + + +abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule { + class TLCDRIO extends Bundle{ + val overCLK = Input(Bool()) + val dDatIn = Input(Bool()) + val dDatOut = Output(Bool()) + val uDatIn = Input(Bool()) + val uDatOut = Output(Bool()) + + val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle))) + val tld = new DecoupledIO(new TLBundleD(edge.bundle)) + + val interrupt = Output(Vec(4, Bool())) + } + + val io: TLCDRIO = IO(new TLCDRIO) + + val dirSel = RegInit(false.B) + + val CDRIn = Module(new CDRIn) + CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn ) + CDRIn.io.overCLK := io.overCLK + + val CDROut = Module(new CDROut) + io.dDatOut := ~dirSel & CDROut.io.serDat + io.uDatOut := dirSel & CDROut.io.serDat + + + + val txFifo = Module(new Queue(UInt(32.W), 16)) + val rxFifo = Module(new Queue(UInt(32.W), 16)) + + + // val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) ) + val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + +} + + +trait TL2CDRTx{ this: TL2CDRBase => + + // val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U ) + // val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U ) + // val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U ) + val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) + val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + + + val txLen = RegInit(0.U(12.W)) + val isTxBusy = RegInit(false.B) + val isTxFull = ~txFifo.io.enq.ready + + + val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B) + println("Warning, TxEnd no confident\n") + val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull + val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast + + val txCnt = Reg(UInt(2.W)) + + val txData = Reg(UInt(32.W)) + + when( txFifo.io.deq.fire ){ //txCnt === 3.U + txData := txFifo.io.deq.bits + when( isTxBusy ){ + assert(CDROut.io.axis.fire) + } + + } .elsewhen( CDROut.io.axis.fire ){ + txData := txData << 8 + } + + txFifo.io.deq.ready := + Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B ) + + txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset + CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset + + CDROut.io.axis.bits.tdata := txData.head(8) + + // PriorityMux(Seq( + // (txCnt === 0.U) -> txData(31, 24), + // (txCnt === 1.U) -> txData(23, 16), + // (txCnt === 2.U) -> txData(15, 8), + // (txCnt === 3.U) -> txData( 7, 0), + // )) + + CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U + CDROut.io.axis.bits.tuser := false.B + CDROut.io.axis.valid := isTxBusy + + + when( isTLWriteTxLen | isTLWriteSoftReset ){ + isTxBusy := false.B + }.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){ + isTxBusy := true.B + } .elsewhen( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast ){ + isTxBusy := false.B + } + + + when( isTLWriteTxLen ){ + txCnt := 0.U + } .elsewhen( CDROut.io.axis.fire ){ + txCnt := txCnt + 1.U + } + + + when( isTLWriteTxLen ){ + // txLen := io.mem.wdata + txLen := io.tla.bits.data + } .elsewhen( CDROut.io.axis.fire ){ + txLen := txLen - 1.U + } + + txFifo.io.enq.bits := io.tla.bits.data + txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U + + +} + + +trait TL2CDRRx{ this: TL2CDRBase => + + // val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U ) + // val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U ) + // val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U ) + + // val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) + val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) + val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) + + + val rxLen = RegInit(0.U(12.W)) + val isRxValid = rxFifo.io.enq.fire + val isRxError = RegInit(false.B) + val isAxisEnd = RegInit(false.B) + val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid + + val intRxError = ~RegNext(isRxError, false.B) & isRxError + val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire + val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd + + + val rxCnt = RegInit(0.U(2.W)) + val rxData = Reg(UInt(24.W)) + + when( isTLWriteSoftReset ){ + isAxisEnd := false.B + } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){ + isAxisEnd := true.B + } + + + when( isTLWriteSoftReset ){ + rxCnt := 0.U + } .elsewhen( CDRIn.io.axis.fire ){ + rxCnt := rxCnt + 1.U + + rxData := Cat( rxData, CDRIn.io.axis.bits.tdata ) + } + + when( isTLWriteSoftReset ){ + rxLen := 0.U + } .elsewhen( CDRIn.io.axis.fire ){ + rxLen := rxLen + 1.U + } + + rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U + rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ) + + assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) + + CDRIn.io.axis.ready := true.B + + rxFifo.reset := reset.asBool | isTLWriteSoftReset + CDRIn.reset := reset.asBool | isTLWriteSoftReset + + rxFifo.io.deq.ready := isTLReadRxFifo + + + when( isTLWriteSoftReset ){ + isRxError := false.B + } .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){ + isRxError := true.B + printf("Warning, RxFifo Overflow!\n") + } + + + +} + +class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) with TL2CDRTx with TL2CDRRx{ + + // val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U + val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + + val tlaInfo = Reg(new TLBundleA(edge.bundle)) + val rdata = Reg(UInt(32.W)) + val tlAReady = RegInit(true.B) + val tlDValid = RegInit(false.B) + + val isRead = tlaInfo.opcode === 4.U + + when( isWriteTransDir ){ + // dirSel := io.mem.wdata + dirSel := io.tla.bits.data + } + + // io.mem.ready := + // ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | + // ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) ) + + io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) ) + io.tld.valid := tlDValid + + io.interrupt(0) := intTxEnd + io.interrupt(1) := intRxError + io.interrupt(2) := intRxStart + io.interrupt(3) := intRxEnd + + + // io.mem.rdata := + // Mux1H(Seq( + // isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B), + // isTLReadRxLen -> rxLen, + // isTLReadRxFifo -> rxFifo.io.deq.bits + // )) + + when( io.tla.fire ) { + tlaInfo := io.tla.bits + } + + when( io.tla.fire ){ + tlAReady := false.B + tlDValid := true.B + } .elsewhen( io.tld.fire ) { + tlAReady := true.B + tlDValid := false.B + } + + when(isRead) { + io.tld.bits := edge.AccessAck(tlaInfo, rdata) + } .otherwise { + io.tld.bits := edge.AccessAck(tlaInfo) + } + + when( isTLReadStatus){ + rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B ) + } .elsewhen(isTLReadRxLen ){ + rdata := rxLen + } .elsewhen(isTLReadRxFifo ){ + rdata := rxFifo.io.deq.bits + } + + +} + + diff --git a/src/main/scala/backBoard/ebus/b4b5.scala b/src/main/scala/backBoard/ebus/b4b5.scala index 3cea1c6..6ede6a2 100644 --- a/src/main/scala/backBoard/ebus/b4b5.scala +++ b/src/main/scala/backBoard/ebus/b4b5.scala @@ -1,65 +1,65 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -object b4b5Encoder{ - def apply( enq: UInt ): UInt = { - Mux1H(Seq( - (enq === "b0000".U) -> "b11110".U(5.W), - (enq === "b0001".U) -> "b01001".U(5.W), - (enq === "b0010".U) -> "b10100".U(5.W), - (enq === "b0011".U) -> "b10101".U(5.W), - (enq === "b0100".U) -> "b01010".U(5.W), - (enq === "b0101".U) -> "b01011".U(5.W), - (enq === "b0110".U) -> "b01110".U(5.W), - (enq === "b0111".U) -> "b01111".U(5.W), - (enq === "b1000".U) -> "b10010".U(5.W), - (enq === "b1001".U) -> "b10011".U(5.W), - (enq === "b1010".U) -> "b10110".U(5.W), - (enq === "b1011".U) -> "b10111".U(5.W), - (enq === "b1100".U) -> "b11010".U(5.W), - (enq === "b1101".U) -> "b11011".U(5.W), - (enq === "b1110".U) -> "b11100".U(5.W), - (enq === "b1111".U) -> "b11101".U(5.W), - )) - } -} - -object b4b5Decoder{ - def apply( enq: UInt ): UInt = { - Mux1H(Seq( - (enq === "b11110".U) -> "b0000".U(4.W), - (enq === "b01001".U) -> "b0001".U(4.W), - (enq === "b10100".U) -> "b0010".U(4.W), - (enq === "b10101".U) -> "b0011".U(4.W), - (enq === "b01010".U) -> "b0100".U(4.W), - (enq === "b01011".U) -> "b0101".U(4.W), - (enq === "b01110".U) -> "b0110".U(4.W), - (enq === "b01111".U) -> "b0111".U(4.W), - (enq === "b10010".U) -> "b1000".U(4.W), - (enq === "b10011".U) -> "b1001".U(4.W), - (enq === "b10110".U) -> "b1010".U(4.W), - (enq === "b10111".U) -> "b1011".U(4.W), - (enq === "b11010".U) -> "b1100".U(4.W), - (enq === "b11011".U) -> "b1101".U(4.W), - (enq === "b11100".U) -> "b1110".U(4.W), - (enq === "b11101".U) -> "b1111".U(4.W), - )) - } -} - -object Dualb4b5Encoder{ - def apply( enq: UInt ): UInt = { - require( enq.width == 8 ) - Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) ) - } -} - -object Dualb4b5Decoder{ - def apply( enq: UInt ): UInt = { - require( enq.width == 10 ) - Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(5,0)) ) - } -} +package BACK + +import chisel3._ +import chisel3.util._ + + +object b4b5Encoder{ + def apply( enq: UInt ): UInt = { + Mux1H(Seq( + (enq === "b0000".U) -> "b11110".U(5.W), + (enq === "b0001".U) -> "b01001".U(5.W), + (enq === "b0010".U) -> "b10100".U(5.W), + (enq === "b0011".U) -> "b10101".U(5.W), + (enq === "b0100".U) -> "b01010".U(5.W), + (enq === "b0101".U) -> "b01011".U(5.W), + (enq === "b0110".U) -> "b01110".U(5.W), + (enq === "b0111".U) -> "b01111".U(5.W), + (enq === "b1000".U) -> "b10010".U(5.W), + (enq === "b1001".U) -> "b10011".U(5.W), + (enq === "b1010".U) -> "b10110".U(5.W), + (enq === "b1011".U) -> "b10111".U(5.W), + (enq === "b1100".U) -> "b11010".U(5.W), + (enq === "b1101".U) -> "b11011".U(5.W), + (enq === "b1110".U) -> "b11100".U(5.W), + (enq === "b1111".U) -> "b11101".U(5.W), + )) + } +} + +object b4b5Decoder{ + def apply( enq: UInt ): UInt = { + Mux1H(Seq( + (enq === "b11110".U) -> "b0000".U(4.W), + (enq === "b01001".U) -> "b0001".U(4.W), + (enq === "b10100".U) -> "b0010".U(4.W), + (enq === "b10101".U) -> "b0011".U(4.W), + (enq === "b01010".U) -> "b0100".U(4.W), + (enq === "b01011".U) -> "b0101".U(4.W), + (enq === "b01110".U) -> "b0110".U(4.W), + (enq === "b01111".U) -> "b0111".U(4.W), + (enq === "b10010".U) -> "b1000".U(4.W), + (enq === "b10011".U) -> "b1001".U(4.W), + (enq === "b10110".U) -> "b1010".U(4.W), + (enq === "b10111".U) -> "b1011".U(4.W), + (enq === "b11010".U) -> "b1100".U(4.W), + (enq === "b11011".U) -> "b1101".U(4.W), + (enq === "b11100".U) -> "b1110".U(4.W), + (enq === "b11101".U) -> "b1111".U(4.W), + )) + } +} + +object Dualb4b5Encoder{ + def apply( enq: UInt ): UInt = { + require( enq.getWidth == 8 ) + Cat( b4b5Encoder(enq(7,4)), b4b5Encoder(enq(3,0)) ) + } +} + +object Dualb4b5Decoder{ + def apply( enq: UInt ): UInt = { + require( enq.getWidth == 10 ) + Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(5,0)) ) + } +} diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index 715bc09..8d31482 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -11,27 +11,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.gpio._ -abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record } -abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters -case object BackParamsKey extends Field[BackSetting] - -case class BackSetting( -){ - -} - -trait HasBackParameters { - implicit val p: Parameters - - val backSetting = p(BackParamsKey) -} - - - -class BackCfg extends Config((_, _, _) => { - case BackParamsKey => BackSetting() -})