compile without tl2cdr

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -45,7 +45,8 @@ trait CDRInOverSample{ this: CDRInBase =>
   // val syncSerDat = 
   //   Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
 
-  val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)); arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) ) }
+  val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
+  arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) )
   val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
   when( sampleReg(0) ^ sampleReg(1) ){
     arbLock := arbCnt

src/main/scala/backBoard/ebus/TL2CDR.scala

@@ -7,6 +7,32 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
+abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
+abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
+
+case object BackParamsKey extends Field[BackSetting]
+
+case class BackSetting(
+){
+
+}
+
+trait HasBackParameters {
+  implicit val p: Parameters
+
+  val backSetting = p(BackParamsKey)
+}
+
+
+
+class BackCfg extends Config((_, _, _) => {
+  case BackParamsKey => BackSetting()
+})
+
+
+
+
+
 
 abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
   class TLCDRIO extends Bundle{
@@ -117,12 +143,13 @@ trait TL2CDRTx{ this: TL2CDRBase =>
 
 
   when( isTLWriteTxLen ){
-    txLen := io.mem.wdata
+    // txLen := io.mem.wdata
+    txLen := io.tla.bits.data
   } .elsewhen( CDROut.io.axis.fire ){
     txLen := txLen - 1.U
   }
 
-  txFifo.io.enq.bits  := io.mem.wdata
+  txFifo.io.enq.bits  := io.tla.bits.data
   txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
 
 
@@ -199,7 +226,7 @@ trait TL2CDRRx{ this: TL2CDRBase =>
 
 }
 
-class TL2CDR()(implicit p: Parameters) extends TL2CDRBase() with TL2CDRTx with TL2CDRRx{
+class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) with TL2CDRTx with TL2CDRRx{
 
   // val isWriteTransDir       = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
   val isWriteTransDir       = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
@@ -255,7 +282,7 @@ class TL2CDR()(implicit p: Parameters) extends TL2CDRBase() with TL2CDRTx with T
   }
   
   when( isTLReadStatus){
-    rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError )
+    rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B )
   } .elsewhen(isTLReadRxLen       ){
     rdata := rxLen
   } .elsewhen(isTLReadRxFifo      ){

src/main/scala/backBoard/ebus/b4b5.scala

@@ -52,14 +52,14 @@ object b4b5Decoder{
 
 object Dualb4b5Encoder{
   def apply( enq: UInt ): UInt = {
-    require( enq.width == 8 )
+    require( enq.getWidth == 8 )
     Cat( b4b5Encoder(enq(7,4)),  b4b5Encoder(enq(3,0)) )
   }
 }
 
 object Dualb4b5Decoder{
   def apply( enq: UInt ): UInt = {
-    require( enq.width == 10 )
+    require( enq.getWidth == 10 )
     Cat( b4b5Decoder(enq(9,5)),  b4b5Decoder(enq(5,0)) )
   }
 }

src/main/scala/backBoard/pico/BackSystem.scala

@@ -11,27 +11,7 @@ import sifive.blocks.devices.uart._
 import sifive.blocks.devices.gpio._
 
 
-abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
-abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
 
-case object BackParamsKey extends Field[BackSetting]
-
-case class BackSetting(
-){
-
-}
-
-trait HasBackParameters {
-  implicit val p: Parameters
-
-  val backSetting = p(BackParamsKey)
-}
-
-
-
-class BackCfg extends Config((_, _, _) => {
-  case BackParamsKey => BackSetting()
-})