compile without tl2cdr
This commit is contained in:
Ruige Lee (WSL)
@@ -1,109 +1,109 @@
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package BACK
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import chisel3._
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import chisel3.util._
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class AXIS_Bundle(dw: Int) extends Bundle{
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val tdata = UInt(dw.W)
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val tlast = Bool()
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val tuser = Bool()
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}
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//work in 100MHZ
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class CDROutIO extends Bundle{
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val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
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val serDat = Output(Bool())
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}
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class CDROut extends Module{
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val io: CDROutIO = IO(new CDROutIO)
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val crcUnit = Module(new crc32_8)
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def STATE_IDLE = 0.U
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def STATE_PREAMBLE = 1.U
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def STATE_PAYLOAD = 2.U
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def STATE_FCS = 3.U
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val ETH_PRE = "h55".U
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val ETH_SFD = "hD5".U
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, 0.U )
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = Reg(UInt(3.W)) //payload dont need to count
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val crcOut = crcUnit.io.crc
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val reset_crc = stateCurr === STATE_IDLE
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crcUnit.reset := reset.asBool | reset_crc
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crcUnit.io.dataIn := io.axis.bits.tdata
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crcUnit.io.isEnable := io.axis.fire
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val shiftData = RegInit(0.U(10.W))
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stateNext := Mux1H(Seq(
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(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
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(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
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(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
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(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
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))
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io.serDat := shiftData.extract(9)
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io.axis.ready :=
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bitCnt === 9.U & (
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(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
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(stateCurr === STATE_PAYLOAD)
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)
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when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
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shiftData := Dualb4b5Encoder(ETH_PRE)
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} .otherwise{
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when( bitCnt =/= 9.U ){
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shiftData := shiftData << 1
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} .otherwise{ //bitCnt === 9.U
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when( stateCurr === STATE_PREAMBLE ){
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shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
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( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
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( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
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))
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
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} .elsewhen( stateCurr === STATE_FCS ){
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shiftData := Mux1H(Seq(
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( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
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( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
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( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
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( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
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))
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}
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}
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}
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when( stateCurr === STATE_IDLE ){ //PRE
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bitCnt := 0.U
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} .otherwise{
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when( bitCnt === 9.U ){
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bitCnt := 0.U
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} .otherwise{
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bitCnt := bitCnt + 1.U
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}
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}
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when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
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byteCnt := 0.U
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} .elsewhen( bitCnt === 9.U ){
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byteCnt := byteCnt + 1.U
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}
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}
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package BACK
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import chisel3._
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import chisel3.util._
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class AXIS_Bundle(dw: Int) extends Bundle{
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val tdata = UInt(dw.W)
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val tlast = Bool()
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val tuser = Bool()
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}
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//work in 100MHZ
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class CDROutIO extends Bundle{
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val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
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val serDat = Output(Bool())
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}
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class CDROut extends Module{
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val io: CDROutIO = IO(new CDROutIO)
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val crcUnit = Module(new crc32_8)
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def STATE_IDLE = 0.U
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def STATE_PREAMBLE = 1.U
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def STATE_PAYLOAD = 2.U
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def STATE_FCS = 3.U
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val ETH_PRE = "h55".U
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val ETH_SFD = "hD5".U
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, 0.U )
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = Reg(UInt(3.W)) //payload dont need to count
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val crcOut = crcUnit.io.crc
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val reset_crc = stateCurr === STATE_IDLE
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crcUnit.reset := reset.asBool | reset_crc
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crcUnit.io.dataIn := io.axis.bits.tdata
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crcUnit.io.isEnable := io.axis.fire
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val shiftData = RegInit(0.U(10.W))
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stateNext := Mux1H(Seq(
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(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
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(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
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(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
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(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
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))
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io.serDat := shiftData.extract(9)
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io.axis.ready :=
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bitCnt === 9.U & (
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(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
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(stateCurr === STATE_PAYLOAD)
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)
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when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
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shiftData := Dualb4b5Encoder(ETH_PRE)
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} .otherwise{
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when( bitCnt =/= 9.U ){
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shiftData := shiftData << 1
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} .otherwise{ //bitCnt === 9.U
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when( stateCurr === STATE_PREAMBLE ){
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shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
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( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
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( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
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))
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
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} .elsewhen( stateCurr === STATE_FCS ){
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shiftData := Mux1H(Seq(
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( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
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( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
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( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
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( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
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))
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}
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}
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}
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when( stateCurr === STATE_IDLE ){ //PRE
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bitCnt := 0.U
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} .otherwise{
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when( bitCnt === 9.U ){
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bitCnt := 0.U
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} .otherwise{
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bitCnt := bitCnt + 1.U
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}
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}
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when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
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byteCnt := 0.U
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} .elsewhen( bitCnt === 9.U ){
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byteCnt := byteCnt + 1.U
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}
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}
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