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仿真开始

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RuigeLee
2024-10-16 16:17:52 +08:00
parent 55f016d866
commit 0dc046bffe
4 changed files with 253 additions and 6 deletions
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4
src/test/scala/gcd/test.scala
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@@ -46,11 +46,11 @@ object testModule extends App {
// ChiselGeneratorAnnotation(() => { new CDRIn })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinMst })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinSlvBase })
))