From 0dc046bffe23464db077ee0e9bac1db613ca9fb8 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 16 Oct 2024 16:17:52 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=BF=E7=9C=9F=E5=BC=80=E5=A7=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 8 +- src/main/scala/backBoard/shin/ShinSlv.scala | 4 + src/test/scala/gcd/test.scala | 4 +- tb/ShinBack_tb.v | 243 ++++++++++++++++++++ 4 files changed, 253 insertions(+), 6 deletions(-) create mode 100644 tb/ShinBack_tb.v diff --git a/Makefile b/Makefile index 35797eb..9bf4ad5 100644 --- a/Makefile +++ b/Makefile @@ -13,6 +13,7 @@ compile: back: rm -f ./generated/back/* + rm -f ./generated/cdr/* sbt "test:runMain test.testModule" cp ./src/main/verilog/backBoardMstTop.v ./generated/back/ cp ./src/main/verilog/oser_rst.v ./generated/back/ @@ -117,15 +118,14 @@ VSimBack: tb: - cp ./generated/cdr/crc32_8.v ./tb - cp ./generated/cdr/CDRIn.v ./tb - cp ./generated/cdr/CDROut.v ./tb iverilog -Wall \ -o ./build/wave.iverilog \ -y ./tb \ + -y ./generated/cdr/ \ -I ./tb \ + -I ./generated/cdr/ \ -D RANDOMIZE_REG_INIT \ - ./tb/cdrInOut_tb.v + ./tb/ShinBack_tb.v vvp -N ./build/wave.iverilog -lxt2 vcd: diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala index f71ec77..108f260 100644 --- a/src/main/scala/backBoard/shin/ShinSlv.scala +++ b/src/main/scala/backBoard/shin/ShinSlv.scala @@ -532,6 +532,10 @@ with ShinSlvLinkInit with ShinSlvLinkBCast with ShinSlvLinkUCast{ assert( VecInit(upRegMuxInit).count((x:Bool) => (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" ) + + + val led = IO(UInt(8.W)) + led := slvID } diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 26d9a55..9cd5308 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -46,11 +46,11 @@ object testModule extends App { // ChiselGeneratorAnnotation(() => { new CDRIn }) // )) - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq( + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( ChiselGeneratorAnnotation(() => { new ShinMst }) )) - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq( + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( ChiselGeneratorAnnotation(() => { new ShinSlvBase }) )) diff --git a/tb/ShinBack_tb.v b/tb/ShinBack_tb.v new file mode 100644 index 0000000..525b9f8 --- /dev/null +++ b/tb/ShinBack_tb.v @@ -0,0 +1,243 @@ + +`timescale 1 ns / 1 ps + + + + + +module ShinBack_tb(); + + + reg clock = 0; + reg overClk = 0; + reg reset = 0; + + reg [15:0] io_FSMC_ADIn; + wire [15:0] io_FSMC_ADOut; + wire io_FSMC_ADOEn; + reg io_FSMC_csn = 1; + reg io_FSMC_rdn = 1; + reg io_FSMC_wrn = 1; + reg io_FSMC_advn; + + + reg io_testIO = 0; + + wire [3:0] downStreamDat; + wire [3:0] upStreamDat; + + + ShinMst s_shinMst( + .clock(clock), + .reset(reset), + + .io_FSMC_ADIn(io_FSMC_ADIn), + .io_FSMC_ADOut(io_FSMC_ADOut), + .io_FSMC_ADOEn(io_FSMC_ADOEn), + .io_FSMC_csn(io_FSMC_csn), + .io_FSMC_rdn(io_FSMC_rdn), + .io_FSMC_wrn(io_FSMC_wrn), + .io_FSMC_advn(io_FSMC_advn), + .io_interrupt(), + .io_testIO(io_testIO), + + .io_serOut(downStreamDat[0]), + .io_serIn(upStreamDat[0]), + .io_overCLK(overClk) + ); + + ShinSlvBase s_ShinSlv0( + .clock(clock), + .reset(reset), + .io_isOnline(), + .io_isLast(1'b0), + .io_DCIn(1'b0), + .io_downSer_out(downStreamDat[1]), + .io_downSer_in(downStreamDat[0]), + .io_upSer_out(upStreamDat[0]), + .io_upSer_in(upStreamDat[1]), + .io_overCLK(overClk), + .led() + ); + + ShinSlvBase s_ShinSlv1( + .clock(clock), + .reset(reset), + .io_isOnline(), + .io_isLast(1'b0), + .io_DCIn(1'b0), + .io_downSer_out(downStreamDat[2]), + .io_downSer_in(downStreamDat[1]), + .io_upSer_out(upStreamDat[1]), + .io_upSer_in(upStreamDat[2]), + .io_overCLK(overClk), + .led() + ); + + ShinSlvBase s_ShinSlv2( + .clock(clock), + .reset(reset), + .io_isOnline(), + .io_isLast(1'b0), + .io_DCIn(1'b0), + .io_downSer_out(downStreamDat[3]), + .io_downSer_in(downStreamDat[2]), + .io_upSer_out(upStreamDat[2]), + .io_upSer_in(upStreamDat[3]), + .io_overCLK(overClk), + .led() + ); + + ShinSlvBase s_ShinSlv3( + .clock(clock), + .reset(reset), + .io_isOnline(), + .io_isLast(1'b0), + .io_DCIn(1'b0), + .io_downSer_out(), + .io_downSer_in(downStreamDat[3]), + .io_upSer_out(upStreamDat[3]), + .io_upSer_in(1'b0), + .io_overCLK(overClk), + .led() + ); + + + + +initial begin + forever #80 clock = ~clock; +end + +initial begin + #10 + forever #20 overClk = ~overClk; +end + +initial begin + # 100 reset = 1; + # 100 reset = 0; +end + + +initial begin + + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 1; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 1; + io_testIO = 0; + + #1000 + + +// @0 <- 512 length | operator + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 0; + + #100 + io_FSMC_ADIn = 16'd512 << 8 | 16'd0; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 0; + io_FSMC_advn = 1; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 1; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 1; + +// @1 <- 0 param0 + #100 + io_FSMC_ADIn = 16'd1; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 0; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 0; + io_FSMC_advn = 1; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 1; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 1; + +// @2 <- 0 param1 + #100 + io_FSMC_ADIn = 16'd2; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 0; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 0; + io_FSMC_advn = 1; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 1; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 1; + +// @3 <- 0 param2 + #100 + io_FSMC_ADIn = 16'd3; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 0; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 0; + io_FSMC_rdn = 1; + io_FSMC_wrn = 0; + io_FSMC_advn = 1; + + #100 + io_FSMC_ADIn = 16'd0; + io_FSMC_csn = 1; + io_FSMC_rdn = 1; + io_FSMC_wrn = 1; + io_FSMC_advn = 1; + + + #200 + io_testIO = 1; + #80 + io_testIO = 0; +end + + + + initial begin + # 100000 + $finish; + end + + initial begin + $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 + $dumpvars(0, ShinBack_tb);//tb模块名称 + end + + +endmodule