仿真开始

src/main/scala/backBoard/shin/ShinSlv.scala

@@ -532,6 +532,10 @@ with ShinSlvLinkInit
 with ShinSlvLinkBCast
 with ShinSlvLinkUCast{
   assert( VecInit(upRegMuxInit).count((x:Bool) => (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" )
+
+
+  val led = IO(UInt(8.W))
+  led := slvID
 }
 
 

src/test/scala/gcd/test.scala

@@ -46,11 +46,11 @@ object testModule extends App {
   //     ChiselGeneratorAnnotation(() => { new CDRIn })
   //   ))
 
-   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
+   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new ShinMst })
     ))
 
-   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
+   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new ShinSlvBase })
     ))