仿真开始

Makefile

@@ -13,6 +13,7 @@ compile:
 
 back:
 	rm -f ./generated/back/*
+	rm -f ./generated/cdr/*
 	sbt "test:runMain test.testModule"
 	cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
 	cp ./src/main/verilog/oser_rst.v ./generated/back/
@@ -117,15 +118,14 @@ VSimBack:
 
 
 tb:
-	cp ./generated/cdr/crc32_8.v ./tb
-	cp ./generated/cdr/CDRIn.v ./tb
-	cp ./generated/cdr/CDROut.v ./tb
 	iverilog -Wall \
 	-o ./build/wave.iverilog  \
 	-y ./tb  \
+	-y ./generated/cdr/  \
 	-I ./tb  \
+	-I ./generated/cdr/  \
 	-D RANDOMIZE_REG_INIT \
-	./tb/cdrInOut_tb.v 
+	./tb/ShinBack_tb.v 
 	vvp  -N ./build/wave.iverilog -lxt2
 
 vcd: