看门狗特性

src/main/scala/backBoard/shin/Interface.scala

@@ -33,8 +33,9 @@ class CommonRegisterBundle extends Bundle{
 
 
 
-  // val wdtStatus   = UInt(16.W)
-  // val wdtOverflow = UInt(8.W)
+  val wdtStatus = UInt(32.W)
+  val wdtEnable = UInt(32.W)
+  val wdtTarCnt = Vec( 17, UInt(32.W) )
 
   val timeStamp = UInt(64.W)
   val mstDeltaTime = UInt(32.W)
@@ -45,8 +46,6 @@ class CommonRegisterBundle extends Bundle{
   val custom = Vec( 128, UInt(8.W) )
 
 
-  // val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
-  // val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
   val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
 
@@ -57,8 +56,6 @@ class MasterRegisterBundle extends Bundle{
 
   val txSM         = UInt(2.W)
   val rxSM         = UInt(2.W)
-  // val txLength     = UInt(12.W)
-  // val txStatus     = UInt(16.W)
 
   val rplTimeStampTx = UInt(16.W)
 
@@ -137,7 +134,6 @@ class InterfaceIO extends Bundle{
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
     val rxSM = UInt(2.W)
-    // val txLength = UInt(12.W)
   }) //发送请求和SM代号
 
 
@@ -178,6 +174,8 @@ class InterfaceIO extends Bundle{
   val intSlvTrig  = Input(Vec(8, Bool()))
 
   val interrupt = Output(Bool())
+
+  val wdtTrigger = Input(Vec(17, Bool()))
 }
 
 
@@ -372,6 +370,16 @@ abstract class InterfaceBase extends Module{
       ( 0 until 8 ).map{ i =>
         ( addr === ("h303".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
       } ++
+
+      ( 0 until 4 ).map{ i =>
+        ( addr === ("h400".U(16.W) + i.U) )  -> cReg.wdtStatus( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 4 ).map{ i =>
+        ( addr === ("h404".U(16.W) + i.U) )  -> cReg.wdtEnable( 8*i+7, 8*i+0 )
+      } ++
+      (for( i <- 0 until 17; j <- 0 until 4 ) yield {
+        ( addr === ("h408".U(16.W) + (4*i+j).U) )  -> cReg.wdtTarCnt(i)( 8*j+7, 8*j+0 )
+      }) ++
       Seq()
     )
 
@@ -552,6 +560,45 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   }
 
 
+  val wdtStatus = for( i <- 0 until 17 ) yield { RegInit(false.B) }
+  cReg.wdtStatus := Cat( wdtStatus.reverse )
+
+  for( i <- 0 until 8 ){
+    when( isEnW & addrw === "h400".U & dataw.extract(i) ){
+      wdtStatus(i) := false.B
+    } .elsewhen(io.wdtTrigger(i)){
+      wdtStatus(i) := true.B
+    }
+    when( isEnW & addrw === "h401".U & dataw.extract(i) ){
+      wdtStatus(8+i) := false.B
+    } .elsewhen(io.wdtTrigger(8+i)){
+      wdtStatus(8+i) := true.B
+    }
+  }
+  for( i <- 0 until 1 ){
+    when( isEnW & addrw === "h402".U & dataw.extract(i) ){
+      wdtStatus(16+i) := false.B
+    } .elsewhen(io.wdtTrigger(16+i)){
+      wdtStatus(16+i) := true.B
+    }
+  }
+
+  cReg.wdtEnable := 
+    Cat(
+      RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h406".U ),
+      RegEnable( dataw,            0.U, isEnW & addrw === "h405".U ),
+      RegEnable( dataw,            0.U, isEnW & addrw === "h404".U ),
+    )
+
+  for( i <- 0 until 17 ){
+    cReg.wdtTarCnt(i) :=
+      Cat(
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
+      )
+  }
 
 }
 
@@ -744,6 +791,10 @@ trait InterfaceSync{ this: InterfaceBase =>
 
 }
 
+// trait InterfaceWdt{ this: InterfaceBase =>
+
+// }
+
 trait InterfaceSystem{ this: InterfaceBase =>
   io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
 
@@ -784,8 +835,10 @@ trait InterfaceSystem{ this: InterfaceBase =>
   //主站发送周期到了
 
 
-  //主站接收看门狗溢出
-
+  //看门狗溢出
+  when( io.wdtTrigger.reduce(_|_) & cReg.intEnable(4) ){
+    intStatus(4) := true.B
+  }
 
 
 
@@ -859,6 +912,7 @@ with InterfaceMCUop
 with InterfaceCheckSM
 with InterfaceLVDSop
 with InterfaceSync
+// with InterfaceWdt
 with InterfaceSystem
 {