diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index e43ce2d..8cbb71e 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -33,8 +33,9 @@ class CommonRegisterBundle extends Bundle{
 
 
 
-  // val wdtStatus   = UInt(16.W)
-  // val wdtOverflow = UInt(8.W)
+  val wdtStatus = UInt(32.W)
+  val wdtEnable = UInt(32.W)
+  val wdtTarCnt = Vec( 17, UInt(32.W) )
 
   val timeStamp = UInt(64.W)
   val mstDeltaTime = UInt(32.W)
@@ -45,8 +46,6 @@ class CommonRegisterBundle extends Bundle{
   val custom = Vec( 128, UInt(8.W) )
 
 
-  // val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
-  // val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
   val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
 
@@ -57,8 +56,6 @@ class MasterRegisterBundle extends Bundle{
 
   val txSM         = UInt(2.W)
   val rxSM         = UInt(2.W)
-  // val txLength     = UInt(12.W)
-  // val txStatus     = UInt(16.W)
 
   val rplTimeStampTx = UInt(16.W)
 
@@ -137,7 +134,6 @@ class InterfaceIO extends Bundle{
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
     val rxSM = UInt(2.W)
-    // val txLength = UInt(12.W)
   }) //发送请求和SM代号
 
 
@@ -178,6 +174,8 @@ class InterfaceIO extends Bundle{
   val intSlvTrig  = Input(Vec(8, Bool()))
 
   val interrupt = Output(Bool())
+
+  val wdtTrigger = Input(Vec(17, Bool()))
 }
 
 
@@ -372,6 +370,16 @@ abstract class InterfaceBase extends Module{
       ( 0 until 8 ).map{ i =>
         ( addr === ("h303".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
       } ++
+
+      ( 0 until 4 ).map{ i =>
+        ( addr === ("h400".U(16.W) + i.U) )  -> cReg.wdtStatus( 8*i+7, 8*i+0 )
+      } ++
+      ( 0 until 4 ).map{ i =>
+        ( addr === ("h404".U(16.W) + i.U) )  -> cReg.wdtEnable( 8*i+7, 8*i+0 )
+      } ++
+      (for( i <- 0 until 17; j <- 0 until 4 ) yield {
+        ( addr === ("h408".U(16.W) + (4*i+j).U) )  -> cReg.wdtTarCnt(i)( 8*j+7, 8*j+0 )
+      }) ++
       Seq()
     )
 
@@ -552,6 +560,45 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   }
 
 
+  val wdtStatus = for( i <- 0 until 17 ) yield { RegInit(false.B) }
+  cReg.wdtStatus := Cat( wdtStatus.reverse )
+
+  for( i <- 0 until 8 ){
+    when( isEnW & addrw === "h400".U & dataw.extract(i) ){
+      wdtStatus(i) := false.B
+    } .elsewhen(io.wdtTrigger(i)){
+      wdtStatus(i) := true.B
+    }
+    when( isEnW & addrw === "h401".U & dataw.extract(i) ){
+      wdtStatus(8+i) := false.B
+    } .elsewhen(io.wdtTrigger(8+i)){
+      wdtStatus(8+i) := true.B
+    }
+  }
+  for( i <- 0 until 1 ){
+    when( isEnW & addrw === "h402".U & dataw.extract(i) ){
+      wdtStatus(16+i) := false.B
+    } .elsewhen(io.wdtTrigger(16+i)){
+      wdtStatus(16+i) := true.B
+    }
+  }
+
+  cReg.wdtEnable := 
+    Cat(
+      RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h406".U ),
+      RegEnable( dataw,            0.U, isEnW & addrw === "h405".U ),
+      RegEnable( dataw,            0.U, isEnW & addrw === "h404".U ),
+    )
+
+  for( i <- 0 until 17 ){
+    cReg.wdtTarCnt(i) :=
+      Cat(
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
+      )
+  }
 
 }
 
@@ -744,6 +791,10 @@ trait InterfaceSync{ this: InterfaceBase =>
 
 }
 
+// trait InterfaceWdt{ this: InterfaceBase =>
+
+// }
+
 trait InterfaceSystem{ this: InterfaceBase =>
   io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
 
@@ -784,8 +835,10 @@ trait InterfaceSystem{ this: InterfaceBase =>
   //主站发送周期到了
 
 
-  //主站接收看门狗溢出
-
+  //看门狗溢出
+  when( io.wdtTrigger.reduce(_|_) & cReg.intEnable(4) ){
+    intStatus(4) := true.B
+  }
 
 
 
@@ -859,6 +912,7 @@ with InterfaceMCUop
 with InterfaceCheckSM
 with InterfaceLVDSop
 with InterfaceSync
+// with InterfaceWdt
 with InterfaceSystem
 {
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 56ca7df..b0beb5b 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -387,10 +387,45 @@ trait ShinTopSlave{ this: ShinTopBase =>
 }
 
 
+trait ShinTopWatchDog{ this: ShinTopBase =>
 
 
+  val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
+  val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
+
+  for( i <- 0 until 8 ){
+    when( smUnit(i).io.enq ){
+      isWdtSMEnable(2*i) := false.B
+    } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){
+      isWdtSMEnable(2*i) := true.B
+    }
+
+    when( smUnit(i).io.deq ){
+      isWdtSMEnable(2*i + 1) := false.B
+    } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){
+      isWdtSMEnable(2*i + 1) := true.B
+    }
+  }
+
+  for( i <- 0 until 16 ){
+    when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){
+      wdtSMCnt(i) := wdtSMCnt(i) + 1.U
+    } .elsewhen( ~isWdtSMEnable(i) ){
+      wdtSMCnt(i) := 0.U
+    }
+
+    assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), "Assert Failed! wdtSMCnt is larger than wdtTarCnt, Special situation?" )
+    
+    interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
+  }
+  interface.io.wdtTrigger(0) := slaveParser.io.isRecWdtTrigger
+
+
+}
+
 
 
 class ShinTop extends ShinTopBase
 with ShinTopMaster
 with ShinTopSlave
+with ShinTopWatchDog
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index ef99210..ba6f4df 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -70,6 +70,8 @@ class SlaveParserIO extends Bundle{
 
   val intHWTrig   = Output(Vec(2, Bool()))
   val intHWClr    = Input (Vec(2, Bool()))
+
+  val isRecWdtTrigger = Output(Bool())
 }
 
 abstract class SlaveParserBase extends Module{
@@ -705,8 +707,9 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
 
 
   // val ProbeRecAim  = 511.U
-  val probeRecCnt = RegInit(0.U(9.W))
-  val isWatchDogOverflow = probeRecCnt.andR
+  val probeRecCnt = RegInit(0.U(32.W))
+  val isWatchDogOverflow = probeRecCnt === io.cReg.wdtTarCnt(0)
+  io.isRecWdtTrigger := isWatchDogOverflow
 
 
 
@@ -749,7 +752,7 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
     probeRecCnt := 0.U
   } .elsewhen( isWatchDogOverflow ){
     probeRecCnt := 0.U
-  } .elsewhen( isReadyToProbe ){
+  } .elsewhen( isReadyToProbe & io.cReg.wdtEnable.extract(0) ){
     probeRecCnt := probeRecCnt + 1.U
   }