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锁定后允许在正负3相位之间校准

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This commit is contained in:
Ruige Lee
2025-08-21 18:57:28 +08:00
parent a20ee39087
commit 06996d6945
1 changed files with 28 additions and 22 deletions
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36
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -113,7 +113,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
val clearCnt = Reg(UInt(4.W))
val checkCnt = Reg(UInt(4.W))
val arbLock = Reg(UInt( (log2Ceil(clkNum)+1).W ))
val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val isLock = RegInit(false.B)
when( sampleReg.reduce(_|_) === false.B ){
@@ -132,27 +133,32 @@ trait CDRInMultiSample{ this: CDRInBase =>
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
for( i <- 0 + 4 until clkNum + 4 ){
val j = clkNum + 4 - i -1
val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
diff := arbLock - j.U
when( flitReg(j) ^ flitReg(j+1) ){
// val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
// diff := arbLock - j.U
when( ~isLock ){
for( i <- 3 until 19 ){
val j = 19 - i - 1
when( flitReg(j) ^ flitReg(j+1) ){
arbLock := j.U
isLock := true.B
arbCali := j.U
}
}
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
when( diff > 8.U ){
arbLock := arbLock + 1.U
} .elsewhen( diff < 8.U ){
arbLock := arbLock - 1.U
for( i <- 0 until 22 ){
val j = 22 - i -1
when( flitReg(j) ^ flitReg(j+1) ){
when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
arbCali := arbCali - 1.U
} .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
arbCali := arbCali + 1.U
}
}
}
}
when( ~isLock ){
for( i <- 0 until clkNum ){
val j = clkNum - i -1
for( i <- 3 until 19 ){
val j = 19 - i - 1
when( flitReg(j) ^ flitReg(j+1) ){
isLock := true.B
}
@@ -164,8 +170,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
val asyncSerDat =
Mux1H(
(for { i <- 4 until clkNum+4 } yield {
(arbLock === i.U) -> flitReg(i+(clkNum/2))
(for { i <- 0 until 22 } yield {
(arbCali === i.U) -> flitReg(i+(8))
})
)