From 06996d69452649a1e2cd6f104ce3b7f561e53a74 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 21 Aug 2025 18:57:28 +0800
Subject: [PATCH] =?UTF-8?q?=E9=94=81=E5=AE=9A=E5=90=8E=E5=85=81=E8=AE=B8?=
 =?UTF-8?q?=E5=9C=A8=E6=AD=A3=E8=B4=9F3=E7=9B=B8=E4=BD=8D=E4=B9=8B?=
 =?UTF-8?q?=E9=97=B4=E6=A0=A1=E5=87=86?=
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---
 src/main/scala/backBoard/ebus/CDRIn.scala | 50 +++++++++++++----------
 1 file changed, 28 insertions(+), 22 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 5379e86..374cf21 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -113,7 +113,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   val clearCnt = Reg(UInt(4.W))
   val checkCnt = Reg(UInt(4.W))
-  val arbLock = Reg(UInt( (log2Ceil(clkNum)+1).W ))
+  val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W ))
+  val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
   val isLock = RegInit(false.B)
 
   when( sampleReg.reduce(_|_) === false.B ){
@@ -132,40 +133,45 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
 
-    for( i <- 0 + 4 until clkNum + 4 ){
-      val j = clkNum + 4 - i -1
-      val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
-      diff := arbLock - j.U
-      when( flitReg(j) ^ flitReg(j+1) ){
-        when( ~isLock ){
-          arbLock := j.U
-          isLock := true.B
-        } .elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
-          when( diff > 8.U ){
-            arbLock := arbLock + 1.U
-          } .elsewhen( diff < 8.U ){
-            arbLock := arbLock - 1.U
+      // val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
+      // diff := arbLock - j.U
+      when( ~isLock ){
+        for( i <- 3 until 19 ){
+          val j = 19 - i - 1
+          when( flitReg(j) ^ flitReg(j+1) ){
+            arbLock := j.U
+            arbCali := j.U
+          }
+        }
+      }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
+        for( i <- 0 until 22 ){
+          val j = 22 - i -1
+          when( flitReg(j) ^ flitReg(j+1) ){
+            when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
+              arbCali := arbCali - 1.U
+            } .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
+              arbCali := arbCali + 1.U
+            }
           }
         }
       }
-    }
-    
-  when( ~isLock ){    
-    for( i <- 0 until clkNum ){
-      val j = clkNum - i -1
+
+  when( ~isLock ){
+    for( i <- 3 until 19 ){
+      val j = 19 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         isLock := true.B
       }
     }
-  }.elsewhen( clearCnt === 10.U ){
+  } .elsewhen( clearCnt === 10.U ){
     isLock := false.B
   }
 
 
   val asyncSerDat = 
     Mux1H(
-      (for { i <- 4 until clkNum+4 } yield {
-        (arbLock === i.U) -> flitReg(i+(clkNum/2))
+      (for { i <- 0 until 22 } yield {
+        (arbCali === i.U) -> flitReg(i+(8))
       })
     )