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上升沿采样，下降沿跳变，应该约束datar到exReg的时间

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RuigeLee
2026-02-13 12:57:01 +08:00
parent 318653f458
commit 051dea4bda
1 changed files with 15 additions and 14 deletions
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29
src/main/scala/backBoard/shin/NSpiInterface.scala
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@@ -12,24 +12,25 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
val io = IO(new RegAccessInterfaceIO) val io = IO(new RegAccessInterfaceIO)
val qspi = IO(new QSPIInterfaceIO) val qspi = IO(new QSPIInterfaceIO)
val posedge_sck = ( qspi.sck).asClock
val negedge_sck = (~qspi.sck).asClock val negedge_sck = (~qspi.sck).asClock
val bitSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) } val bitSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) }
val byteSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))} val byteSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))}
val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val exRegi = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} val exRegi = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))}
val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } }
val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } } val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } }
val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } } val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } } val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } }
val spiLen = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } val spiLen = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiLenTemp = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } val spiLenTemp = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) }
val spiCnt = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) } val spiCnt = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) }
val isSpiWrite = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } val isSpiWrite = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isSpiRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } val isSpiRead = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }
val isPing_async = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } val isPing_async = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }