From 051dea4bda3c8fdba88ead142d26762cd8234e5c Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 13 Feb 2026 12:57:01 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=8A=E5=8D=87=E6=B2=BF=E9=87=87=E6=A0=B7?= =?UTF-8?q?=EF=BC=8C=E4=B8=8B=E9=99=8D=E6=B2=BF=E8=B7=B3=E5=8F=98=EF=BC=8C?= =?UTF-8?q?=E5=BA=94=E8=AF=A5=E7=BA=A6=E6=9D=9Fdatar=E5=88=B0exReg?= =?UTF-8?q?=E7=9A=84=E6=97=B6=E9=97=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/NSpiInterface.scala | 29 ++++++++++--------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala index 53c2426..7ffa690 100644 --- a/src/main/scala/backBoard/shin/NSpiInterface.scala +++ b/src/main/scala/backBoard/shin/NSpiInterface.scala @@ -12,24 +12,25 @@ abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{ val io = IO(new RegAccessInterfaceIO) val qspi = IO(new QSPIInterfaceIO) + val posedge_sck = ( qspi.sck).asClock val negedge_sck = (~qspi.sck).asClock - val bitSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) } - val byteSel = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))} + val bitSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(3.W)) } + val byteSel = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(12.W))} val exRego = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} - val exRegi = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} - val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } - val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } - val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } } - val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } } - val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } } + val exRegi = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){RegInit(0.U(8.W))} + val addrw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } + val addrr_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(16.W)) } } + val dataw_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(8.W)) } } + val isEnR_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } } + val isEnW_async = for( _ <- 0 until 2 ) yield { withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } } - val spiLen = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } - val spiLenTemp = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } - val spiCnt = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) } - val isSpiWrite = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } - val isSpiRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } - val isPing_async = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } + val spiLen = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } + val spiLenTemp = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(2.U(12.W)) } + val spiCnt = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(0.U(12.W)) } + val isSpiWrite = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } + val isSpiRead = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) } + val isPing_async = withClockAndReset(posedge_sck, qspi.csn.asAsyncReset){ RegInit(false.B) }