搭建仿真环境

Makefile

@@ -9,6 +9,7 @@ compile:
 	cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig
 	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v
 	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v
+	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig/plusarg_reader.v ./generated/Rtpp/plusarg_reader.v
 # 	sbt "test:runMain test.testModule"
 
 back:
@@ -33,22 +34,20 @@ VSimTop:
 	rm -rf ./tb/build/
 	mkdir -p ./tb/build/
 	verilator -Wno-fatal  \
-	--timescale "1 ns / 1 ps" \
-	-y ${PWD}/tb/ \
-	-y ${PWD}/tb/vtb/ \
+	-y ${PWD}/generated/Rtpp/ \
+	-y ${PWD}/tb/verilator/ \
 	--top-module SimTop \
 	--trace-fst \
-	--cc ./tb/behav_srams.v   \
-	--cc ./tb/UserFPGAConfig.v \
-	--cc ./tb/vtb/SimTop.v  \
+	--cc ./tb/verilator/SimTop.v  \
+	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
+	--cc ${PWD}/generated/Rtpp/RtppConfig.v  \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
 	+define+RANDOMIZE_INVALID_ASSIGN \
 	+define+RANDOMIZE_REG_INIT \
 	+define+RANDOMIZE_MEM_INIT \
 	+define+RANDOMIZE_DELAY=0 \
-	+define+USE_POWER_PINS \
 	--exe --build \
-	${PWD}/tb/sim_main.cpp \
+	${PWD}/tb/verilator/sim_main.cpp \
 	-Mdir ./tb/build/ \
 	-j 30