From 05162537b6bc9a2f9b8a231e5d45708b0435b550 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 10 Jan 2025 17:14:49 +0800 Subject: [PATCH] =?UTF-8?q?=E6=90=AD=E5=BB=BA=E4=BB=BF=E7=9C=9F=E7=8E=AF?= =?UTF-8?q?=E5=A2=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 15 ++- tb/verilator/SimTop.v | 217 ++++++++++++++++++++++++++++++++++++++ tb/verilator/sim_main.cpp | 183 ++++++++++++++++++++++++++++++++ 3 files changed, 407 insertions(+), 8 deletions(-) create mode 100644 tb/verilator/SimTop.v create mode 100644 tb/verilator/sim_main.cpp diff --git a/Makefile b/Makefile index 9a3264f..a2c18b6 100644 --- a/Makefile +++ b/Makefile @@ -9,6 +9,7 @@ compile: cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v + cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig/plusarg_reader.v ./generated/Rtpp/plusarg_reader.v # sbt "test:runMain test.testModule" back: @@ -33,22 +34,20 @@ VSimTop: rm -rf ./tb/build/ mkdir -p ./tb/build/ verilator -Wno-fatal \ - --timescale "1 ns / 1 ps" \ - -y ${PWD}/tb/ \ - -y ${PWD}/tb/vtb/ \ + -y ${PWD}/generated/Rtpp/ \ + -y ${PWD}/tb/verilator/ \ --top-module SimTop \ --trace-fst \ - --cc ./tb/behav_srams.v \ - --cc ./tb/UserFPGAConfig.v \ - --cc ./tb/vtb/SimTop.v \ + --cc ./tb/verilator/SimTop.v \ + --cc ${PWD}/generated/Rtpp/behav_srams.v \ + --cc ${PWD}/generated/Rtpp/RtppConfig.v \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_DELAY=0 \ - +define+USE_POWER_PINS \ --exe --build \ - ${PWD}/tb/sim_main.cpp \ + ${PWD}/tb/verilator/sim_main.cpp \ -Mdir ./tb/build/ \ -j 30 diff --git a/tb/verilator/SimTop.v b/tb/verilator/SimTop.v new file mode 100644 index 0000000..7e27e64 --- /dev/null +++ b/tb/verilator/SimTop.v @@ -0,0 +1,217 @@ + + + + +/* + Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + + + + + +module SimTop ( + + // output success, + // output fail, + + input clock, //100MHz + input reset, + input clk400, + + input uDatIn, + output uDatOut, + input dDatIn, + output dDatOut +); + + + + + + + +wire dmactive; + +ExampleRocketSystem s_rocket( + .clock(clock), + .reset(reset), + .resetctrl_hartIsInReset_0(reset), + + .debug_clock(clock), + .debug_reset(reset), + .debug_systemjtag_jtag_TCK(1'b0), + .debug_systemjtag_jtag_TMS(1'b0), + .debug_systemjtag_jtag_TDI(1'b0), + .debug_systemjtag_jtag_TDO_data(), + .debug_systemjtag_jtag_TDO_driven(), + .debug_systemjtag_reset(reset), + .debug_systemjtag_mfr_id(11'b0), + .debug_systemjtag_part_number(16'b0), + .debug_systemjtag_version(4'b0), + .debug_ndreset(), + .debug_dmactive(dmactive), + .debug_dmactiveAck(dmactive), + + .mmio_apb_0_psel(), + .mmio_apb_0_penable(), + .mmio_apb_0_pwrite(), + .mmio_apb_0_paddr(), + .mmio_apb_0_pprot(), + .mmio_apb_0_pwdata(), + .mmio_apb_0_pstrb(), + .mmio_apb_0_pready(1'b1), + .mmio_apb_0_pslverr(1'b0), + .mmio_apb_0_prdata(32'b0), + + .mmio_ahb_0_hmastlock(), + .mmio_ahb_0_hsel(), + .mmio_ahb_0_hready(), + .mmio_ahb_0_hreadyout(1'b1), + .mmio_ahb_0_htrans(), + .mmio_ahb_0_hsize(), + .mmio_ahb_0_hburst(), + .mmio_ahb_0_hwrite(), + .mmio_ahb_0_hprot(), + .mmio_ahb_0_haddr(), + .mmio_ahb_0_hwdata(), + .mmio_ahb_0_hresp(2'b0), + .mmio_ahb_0_hrdata(32'b0), + .mmio_ahb_0_hmaster(), + .mmio_ahb_0_hsplit(16'b0), + + .interrupts(2'b0), + + .cdrio_overCLK(clk400), + .cdrio_uDatIn(uDatIn), + .cdrio_uDatOut(uDatOut), + .cdrio_dDatIn(dDatIn), + .cdrio_dDatOut(dDatOut) +); + + + + + + +// wire debugger_success; + +// debuger i_debuger( +// .success(debugger_success), +// .DEBUGER_AWID (mmio_axi4_0_aw_bits_id), +// .DEBUGER_BID (mmio_axi4_0_b_bits_id), +// .DEBUGER_ARID (mmio_axi4_0_ar_bits_id), +// .DEBUGER_RID (mmio_axi4_0_r_bits_id), + +// .DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr), +// .DEBUGER_AWVALID(mmio_axi4_0_aw_valid), +// .DEBUGER_AWREADY(mmio_axi4_0_aw_ready), + +// .DEBUGER_WDATA (mmio_axi4_0_w_bits_data), +// .DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb), +// .DEBUGER_WVALID(mmio_axi4_0_w_valid), +// .DEBUGER_WREADY(mmio_axi4_0_w_ready), + +// .DEBUGER_BRESP (mmio_axi4_0_b_bits_resp), +// .DEBUGER_BVALID(mmio_axi4_0_b_valid), +// .DEBUGER_BREADY(mmio_axi4_0_b_ready), + +// .DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr), +// .DEBUGER_ARVALID(mmio_axi4_0_ar_valid), +// .DEBUGER_ARREADY(mmio_axi4_0_ar_ready), + +// .DEBUGER_RDATA (mmio_axi4_0_r_bits_data), +// .DEBUGER_RRESP (mmio_axi4_0_r_bits_resp), +// .DEBUGER_RVALID(mmio_axi4_0_r_valid), +// .DEBUGER_RREADY(mmio_axi4_0_r_ready), + +// .CLK(CLK), +// .RSTn(RSTn) + +// ); + + + + + + reg [1023:0] firmware_file; + initial begin + if ($value$plusargs("%s", firmware_file)) begin + $display("%s", firmware_file); + $readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram); + end + end + + + + + + + + +// assign success = debugger_success; + + + + +// string testName; + +// `define MEM s_axi_full_slv_sram.i_sram.ram +// reg [7:0] mem [0:200000]; + +// localparam DP = 2**18; +// integer i, by; +// initial begin + +// #20 + +// if ( $value$plusargs("%s",testName) ) begin +// $display("%s",testName); +// $readmemh(testName, mem); + +// end +// else begin +// $display("%s",testName); +// $error("Failed to read Files!"); +// end + + +// for ( i = 0; i < DP; i = i + 1 ) begin +// for ( by = 0; by < 4; by = by + 1 ) begin +// if ( | mem[i*4+by] ) begin +// `MEM[i][8*by +: 8] = mem[i*4+by]; +// end +// else begin +// `MEM[i][8*by +: 8] = 8'h0; +// end +// end +// end + + + +// end + + + + + +endmodule + + + + + + diff --git a/tb/verilator/sim_main.cpp b/tb/verilator/sim_main.cpp new file mode 100644 index 0000000..7980c32 --- /dev/null +++ b/tb/verilator/sim_main.cpp @@ -0,0 +1,183 @@ +/* + Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn> + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +#include +#include "VSimTop.h" +#include +#include +#include + +#include + + + +#if VM_TRACE +#include "verilated_fst_c.h" +#endif + + +char* img; +VSimTop *top; +#if VM_TRACE +VerilatedFstC* tfp; +#endif +vluint64_t main_time = 0; +vluint64_t main_cycle = 0; + +double sc_time_stamp () { + return main_time; +} + + +uint8_t flag_waveEnable = 0; +uint8_t flag_limitEnable = 0; +static void init_and_clock(); + + +int prase_arg(int argc, char **argv) { + int opt; + while( -1 != ( opt = getopt( argc, argv, "pjldwf:" ) ) ) { + switch(opt) { + + case 'l': + flag_limitEnable = 1; + break; + + case 'w': + flag_waveEnable = 1; + std::cout << "Waveform is Enable" << std::endl; + break; + case 'f': + img = strdup(optarg); + // std::cout << "load in image is " << img << std::endl; + break; + case '?': + std::cout << "-w to enable waveform" << std::endl; + std::cout << "-f FILENAME to testfile" << std::endl; + return -1; + break; + default: + std::cout << opt << std::endl; + assert(0); + } + } + return 0; +} + +static void sim_exit(){ +#if VM_TRACE + if ( flag_waveEnable ) { tfp->close(); } +#endif + + top->final(); + delete top; +} + + + + + +int main(int argc, char **argv, char **env) { + + + if ( -1 == prase_arg(argc, argv) ) { + std::cout << "Prase Error." << std::endl; + return -1; + } + + char * temp[2]; + char cmd[64] = "+"; + strcat(cmd, img); + // strcat(cmd, ".hex"); + temp[0] = "Verilated"; + temp[1] = cmd; + char **argv_temp = temp; + Verilated::commandArgs(2, argv_temp); + + + + top = new VSimTop(); + +#if VM_TRACE + tfp = new VerilatedFstC; + if (flag_waveEnable) { + Verilated::traceEverOn(true); + top->trace(tfp, 99); // Trace 99 levels of hierarchy + + tfp->open("./build/wave.fst"); + } +#endif + + + top->reset = 1; + top->clock = 0; + top->clk400 = 0; + + while(!Verilated::gotFinish()) { + + Verilated::timeInc(1); + + init_and_clock(); + + top->eval(); + +#if VM_TRACE + if ( flag_waveEnable ) { tfp->dump(Verilated::time()); } +#endif + + if ( flag_limitEnable ) { + if ( main_cycle > 300000 ){ + std::cout << "Timeout!!!!!" << std::endl; + sim_exit(); + return -1; + } + } + + main_time ++; + } + + sim_exit(); + return -1; + +} + + +static void init_and_clock(){ + + //de-assert reset + if ( main_time != 100 ){ + } else { + top->reset = 0; + } + + //main clock + if ( main_time % 40 == 1 ) { + top->clock = 1; + } else if ( main_time % 40 == 26 ) { + top->clock = 0; + main_cycle ++; + } + + uint8_t phase = 2; + if ( main_time % 10 == (0+phase) ) { + top->clk400 = 1; + } else if ( main_time % 10 == (5+phase) ) { + top->clk400 = 0; + } + + +}