分页制的从机寄存器

2024-04-08 18:49:12 +08:00
parent 0fb012a5e9
commit 0439a67e18
2 changed files with 67 additions and 213 deletions
--- a/src/main/scala/backBoard/BackBoardSlv.scala
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -40,7 +40,7 @@ abstract class BackBoardSlvBase extends Module{

  val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
  val downReg     = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
-  val upReg       = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
+  val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
 }