diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index 6eaad67..a8acac6 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -40,7 +40,7 @@ abstract class BackBoardSlvBase extends Module{ val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)})) val downReg = RegInit(VecInit(Seq.fill(32){0.U(8.W)})) - val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)})) + val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) } diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index f414a15..9d5aae6 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -15,32 +15,46 @@ class ManualParamBundle extends Bundle{ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{ - def DATA_SINWR_ADDR : UInt = "h00".U - def DATA_PERWR_ADDR : UInt = "h02".U - def STATUSWR_ADDR : UInt = "h04".U + // def STATUSWR_ADDR : UInt = "h00".U //01 + // def DATA_PERWR_ADDR : UInt = "h02".U //03 + // def DATA_SINWR_ADDR : UInt = "h04".U //05 - def DATA_SINRD_ADDR : UInt = "h00".U - def DATA_PERRD_ADDR : UInt = "h02".U - def STATUSRD_ADDR : UInt = "h04".U - def VENDORID_ADDR : UInt = "h10".U - def MODULEID_ADDR : UInt = "h12".U - def HVERSION_ADDR : UInt = "h14".U - def SVERSION_ADDR : UInt = "h16".U - def BATCHNUM_ADDR : UInt = "h18".U - def SERIAL0_ADDR : UInt = "h1a".U - def SERIAL1_ADDR : UInt = "h1c".U - def SERIAL2_ADDR : UInt = "h1e".U + // def STATUSRD_ADDR : UInt = "h00".U //01 + // def DATA_PERRD_ADDR : UInt = "h02".U //03 + // def DATA_SINRD_ADDR : UInt = "h04".U //05 + + + + // def VENDORID_ADDR : UInt = "h10".U + // def MODULEID_ADDR : UInt = "h12".U + // def HVERSION_ADDR : UInt = "h14".U + // def SVERSION_ADDR : UInt = "h16".U + // def BATCHNUM_ADDR : UInt = "h18".U + // def SERIAL0_ADDR : UInt = "h1a".U + // def SERIAL1_ADDR : UInt = "h1c".U + // def SERIAL2_ADDR : UInt = "h1e".U val param = IO(Input( new ManualParamBundle )) - val rankNum = downReg(4) - val statusLed = downReg(5)(1,0) + val statusPage = downReg(0)(3,0) + val statusP = RegInit(false.B) + val statusRF = RegInit(false.B) + val statusPR = Cat( downReg(1).extract(0), downReg(0).extract(7) ) + val statusER = RegInit(false.B) + val statusLE = RegInit(false.B) - val (us10Counter, us10Trigger) = Counter(Range(0, 100)) - when( true.B ){ + upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage ) + upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) ) + + when( statusPage === 15.U ){ + upReg(2) := downReg(2) + upReg(3) := downReg(3) + + upReg(4) := downReg(4) + upReg(5) := downReg(5) upReg(16) := param.vendorID(7,0) upReg(17) := param.vendorID(15,8) @@ -66,9 +80,17 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown } + + val (us10Counter, us10Trigger) = Counter(Range(0, 100)) + + } -trait BackBoardSlvStatusLed { this: BackBoardSlvLocal => + + + + +trait BackBoardSlvStatusPR { this: BackBoardSlvLocal => val flashCounter = RegInit( 0.U( 16.W ) ) val flash2HZ = Reg(Bool()) val flash1HZ = Reg(Bool()) @@ -91,10 +113,10 @@ trait BackBoardSlvStatusLed { this: BackBoardSlvLocal => val LED_PR = IO(Output( Bool() )) LED_PR := ~Mux1H(Seq( - ( statusLed === "b00".U ) -> flash2HZ, - ( statusLed === "b01".U ) -> flash1HZ, - ( statusLed === "b10".U ) -> true.B, - ( statusLed === "b11".U ) -> false.B, + ( statusPR === "b00".U ) -> flash2HZ, + ( statusPR === "b01".U ) -> flash1HZ, + ( statusPR === "b10".U ) -> true.B, + ( statusPR === "b11".U ) -> false.B, )) } @@ -104,17 +126,17 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => def gp: Int - val flitCfg = Seq( - // ( 0.U -> 0.S ), - ( 1.U -> (1/2).U), // -> 25.S - ( 2.U -> (2/2).U), // -> 50.S - ( 3.U -> (4/2).U), // -> 100.S - ( 4.U -> (8/2).U), // -> 200.S - ( 5.U -> (16/2).U), // -> 400.S - ( 6.U -> (32/2).U), // -> 800.S - ( 7.U -> (64/2).U), // -> 1600.S - ( 8.U -> (128/2).U), // -> 3200.S - ) + // val flitCfg = Seq( + // // ( 0.U -> 0.S ), + // ( 1.U -> (1/2).U), // -> 25.S + // ( 2.U -> (2/2).U), // -> 50.S + // ( 3.U -> (4/2).U), // -> 100.S + // ( 4.U -> (8/2).U), // -> 200.S + // ( 5.U -> (16/2).U), // -> 400.S + // ( 6.U -> (32/2).U), // -> 800.S + // ( 7.U -> (64/2).U), // -> 1600.S + // ( 8.U -> (128/2).U), // -> 3200.S + // ) val in = IO(Input(UInt((8*gp).W))) @@ -124,9 +146,6 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => flitTrigger(0) := true.B flitTrigger(1) := us10Trigger - // when( ~RegNext(us10Trigger) & us10Trigger ){ - // flitCnt(1) := Mux( flitCnt(1) >= 24.U, 0.U, flitCnt(1) + 1.U ) - // } flitTrigger(2) := flitCnt(2) === 1.U when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){ @@ -165,18 +184,21 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => for( j <- 0 until gp ) { - val digitalFilter = downReg(0+j) - val digitalIn = Wire( Vec(8, Bool()) ) + val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U ) + + val digitalIn = Reg( Vec(8, Bool()) ) + + when( statusPage === 0.U ){ + upReg(2+j) := Cat( digitalIn.reverse ) + upReg(4+j) := downReg(4+j) + } - when(true.B){ upReg( 2+j ) := Cat( digitalIn.reverse ) } for( i <- 0 until 8 ) { val flitter = RegInit(VecInit( Seq.fill(25){false.B})) val flitHi = RegInit(0.U(5.W)) - digitalIn(i) := upReg( 2+j )(i) - ( 0 until 9 ).map{ k => when( digitalFilter === k.U ){ when( flitTrigger(k) ){ @@ -214,9 +236,10 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => class DIn16 extends BackBoardSlvLocal -with BackBoardSlvStatusLed +with BackBoardSlvStatusPR with BackBoardSlvIn{ def gp = 2 + } @@ -240,172 +263,3 @@ class BackBoardSlvOut16 extends BackBoardSlvLocal{ } } - -// trait LocalRegisters { this: BackBoardSlvBase => -// val led = IO(Output(UInt(3.W))) -// val sw = IO( Input(UInt(1.W))) - - - -// val digitalDir = RegInit(0.U(32.W)) -// val digitalOut = RegInit(0.U(32.W)) -// val digitalIn = RegInit(VecInit(Seq.fill(32){false.B})) -// val digitalFilter = RegInit(0.U(2.W)) - - -// val clk100usCnt = RegInit(0.U(13.W)) - -// when( clk100usCnt < 5000.U ){ -// clk100usCnt := clk100usCnt + 1.U -// } .otherwise{ -// clk100usCnt := 0.U -// } - -// for( i <- 0 until 32 ) { -// val hiCnt = RegInit( 0.U( 7.W ) ) -// val loCnt = RegInit( 0.U( 7.W ) ) -// val toCnt = RegInit( 0.U( 7.W ) ) - -// when( digitalFilter === "b00".U ){ -// digitalIn(i) := sw -// } .elsewhen( digitalFilter === "b01".U ){ -// when( clk100usCnt === 5000.U ){ -// when( toCnt === 10.U ){ -// hiCnt := 0.U -// loCnt := 0.U -// toCnt := 0.U -// when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B } -// when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B } -// } .elsewhen( toCnt > 10.U ){ -// hiCnt := 0.U -// loCnt := 0.U -// toCnt := 0.U -// } .otherwise{ -// when(sw === true.B) { hiCnt := hiCnt + 1.U } -// when(sw === false.B) { loCnt := loCnt + 1.U } -// toCnt := toCnt + 1.U -// } -// } -// } .elsewhen( digitalFilter === "b10".U ){ -// when( clk100usCnt === 5000.U ){ -// when( toCnt === 40.U ){ -// hiCnt := 0.U -// loCnt := 0.U -// toCnt := 0.U -// when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B } -// when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B } -// } .elsewhen( toCnt > 40.U ){ -// hiCnt := 0.U -// loCnt := 0.U -// toCnt := 0.U -// } .otherwise{ -// when(sw === true.B) { hiCnt := hiCnt + 1.U } -// when(sw === false.B) { loCnt := loCnt + 1.U } -// toCnt := toCnt + 1.U -// } -// } -// } .elsewhen( digitalFilter === "b11".U ){ -// when( clk100usCnt === 5000.U ){ -// when( toCnt === 80.U ){ -// hiCnt := 0.U -// loCnt := 0.U -// toCnt := 0.U -// when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B } -// when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B } -// } .elsewhen( toCnt > 80.U ){ -// hiCnt := 0.U -// loCnt := 0.U -// toCnt := 0.U -// } .otherwise{ -// when(sw === true.B) { hiCnt := hiCnt + 1.U } -// when(sw === false.B) { loCnt := loCnt + 1.U } -// toCnt := toCnt + 1.U -// } -// } -// } -// } - - - - - -// val pluseCnt = RegInit(0.U(32.W)) - -// val pluseShift = ShiftRegisters( sw, 3, false.B, true.B ) -// when( ~pluseShift(2).asBool & pluseShift(1).asBool ){ -// pluseCnt := pluseCnt + 1.U -// } - -// val pluseAutoCnt = RegInit(0.U(32.W)) -// val pluseAutoFre = RegInit(0.U(32.W)) -// when( clk100usCnt === 5000.U ){ -// pluseAutoCnt := 0.U -// pluseAutoFre := pluseAutoCnt -// } .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){ -// pluseAutoCnt := pluseAutoCnt + 1.U -// } - -// val qeiA = IO(Input(Bool())) -// val qeiB = IO(Input(Bool())) - -// val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B ) -// val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B ) - -// val qeiCnt = RegInit(0.U(32.W)) -// val qeiAutoCnt = RegInit(0.U(32.W)) -// val qeiAutoFre = RegInit(0.U(32.W)) - -// when( ~qeiBShift(2) & qeiBShift(1) ){ -// qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U ) -// qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U ) -// } - - -// when( clk100usCnt === 5000.U ){ -// qeiAutoCnt := 0.U -// qeiAutoFre := qeiAutoCnt -// } .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){ -// qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U ) -// } - - -// registersRD := Mux1H(Seq( -// (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir, -// (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt, -// (upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter, -// (upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt, -// (upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre, -// (upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt, -// (upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre, -// )) - -// when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){ -// when(upStreamReq.io.latDat.bits.register === 0.U){ -// digitalDir := upStreamReq.io.latDat.bits.data -// } -// when(upStreamReq.io.latDat.bits.register === 1.U){ -// digitalOut := upStreamReq.io.latDat.bits.data -// } -// when(upStreamReq.io.latDat.bits.register === 2.U){ -// digitalFilter := upStreamReq.io.latDat.bits.data -// } -// when(upStreamReq.io.latDat.bits.register === 3.U){ -// pluseCnt := upStreamReq.io.latDat.bits.data -// } -// when(upStreamReq.io.latDat.bits.register === 4.U){ -// ; -// } -// when(upStreamReq.io.latDat.bits.register === 5.U){ -// qeiCnt := upStreamReq.io.latDat.bits.data -// } -// when(upStreamReq.io.latDat.bits.register === 6.U){ -// ; -// } -// } - - - - -// led := digitalOut(2,0) -// // digitalIn := sw -// } \ No newline at end of file