ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

没有接入从机情况下，主机初始化将在600us超时

Browse Source
This commit is contained in:
RuigeLee
2024-03-20 11:51:33 +08:00
parent 8b44141214
commit 02d2ef66b7
1 changed files with 13 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -253,6 +253,7 @@ with BackBoardMstFSMC
trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase => trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
val timeoutCnt = Reg(UInt(13.W))
when(ctrlInit){ when(ctrlInit){
when( isInitStart ){ when( isInitStart ){
@@ -275,6 +276,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start } .elsewhen( stateCur === 1.U ){ // tx start
stateCur := 2.U stateCur := 2.U
timeoutCnt := 0.U
frame_info_update_en := false.B frame_info_update_en := false.B
tx_start := true.B tx_start := true.B
@@ -282,6 +284,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
} .elsewhen( stateCur === 2.U ){ } .elsewhen( stateCur === 2.U ){
tx_start := false.B tx_start := false.B
timeoutCnt := timeoutCnt + 1.U
when( lvdsMst.io.slave_link_num_valid ){ when( lvdsMst.io.slave_link_num_valid ){
linkNum := lvdsMst.io.slave_link_num linkNum := lvdsMst.io.slave_link_num
@@ -291,6 +294,16 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
interrupt := true.B interrupt := true.B
} }
when( timeoutCnt === 6000.U ){
linkNum := 0.U
stateCur := 3.U
statusInit := true.B
ctrlInit := false.B
interrupt := true.B
}
} .elsewhen( stateCur === 3.U ){ } .elsewhen( stateCur === 3.U ){
} }