From 02d2ef66b70c8f39e35e53eadb29c744b1c6fadb Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 20 Mar 2024 11:51:33 +0800
Subject: [PATCH] =?UTF-8?q?=E6=B2=A1=E6=9C=89=E6=8E=A5=E5=85=A5=E4=BB=8E?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index e2b0550..ca19cc4 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -253,6 +253,7 @@ with BackBoardMstFSMC
 trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
 
   val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
+  val timeoutCnt = Reg(UInt(13.W))
 
   when(ctrlInit){
     when( isInitStart ){
@@ -275,6 +276,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       tx_start := false.B
     } .elsewhen( stateCur === 1.U ){ // tx start
       stateCur := 2.U
+      timeoutCnt := 0.U
 
       frame_info_update_en := false.B
       tx_start := true.B
@@ -282,6 +284,7 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
     } .elsewhen( stateCur === 2.U ){
 
       tx_start := false.B
+      timeoutCnt := timeoutCnt + 1.U
 
       when( lvdsMst.io.slave_link_num_valid ){
         linkNum := lvdsMst.io.slave_link_num
@@ -291,6 +294,16 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
         interrupt   := true.B
       }
 
+      when( timeoutCnt === 6000.U ){
+        linkNum := 0.U
+        stateCur := 3.U
+        statusInit  := true.B
+        ctrlInit    := false.B
+        interrupt   := true.B
+      }
+
+
+
     } .elsewhen( stateCur === 3.U ){
 
     }