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Revert "cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁"

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This reverts commit d7146a786b.
This commit is contained in:
Ruige Lee
2025-08-20 15:40:25 +08:00
parent b9d255b7ce
commit 0291d445ca
2 changed files with 9 additions and 15 deletions
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12
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -110,12 +110,12 @@ trait CDRInMultiSample{ this: CDRInBase =>
(sampleReg_sync(i+0) & sampleReg_sync(i+1)) (sampleReg_sync(i+0) & sampleReg_sync(i+1))
} }
val clearCnt = Reg(UInt(3.W)) val clearCnt = Reg(UInt(4.W))
val arbLock = Reg(UInt( clkNum.W )) val arbLock = Reg(UInt( clkNum.W ))
val isLock = RegInit(false.B) val isLock = RegInit(false.B)
when( sampleReg.reduce(_|_) === false.B ){ when( sampleReg.reduce(_|_) === false.B ){
when( clearCnt =/= 6.U ){ when( clearCnt =/= 10.U ){
clearCnt := clearCnt + 1.U clearCnt := clearCnt + 1.U
} }
} .otherwise{ } .otherwise{
@@ -132,7 +132,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
isLock := true.B isLock := true.B
} }
} }
} .elsewhen( clearCnt === 6.U ){ } .elsewhen( clearCnt === 10.U ){
isLock := false.B isLock := false.B
} }
@@ -171,7 +171,6 @@ trait CDRInAxis{ this: CDRInBase =>
val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
val shiftData = Dualb4b5Decoder(checkSFD(9,0)) val shiftData = Dualb4b5Decoder(checkSFD(9,0))
val isReleaseLock = checkSFD(9,0) === "b0000000010".U
val payloadLen = RegInit(0.U(12.W)) val payloadLen = RegInit(0.U(12.W))
when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
@@ -207,9 +206,8 @@ trait CDRInAxis{ this: CDRInBase =>
when( stateCurr === STATE_HEADER ){ when( stateCurr === STATE_HEADER ){
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte-1).U ) assert( byteCnt <= (HeaderByte-1).U )
assert(~isReleaseLock)
} .elsewhen( stateCurr === STATE_PAYLOAD ){ } .elsewhen( stateCurr === STATE_PAYLOAD ){
byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), Mux( isReleaseLock, byteCnt, byteCnt + 1.U ), 0.U ) byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
assert( byteCnt <= ( payloadLen+ (4-1).U ) ) assert( byteCnt <= ( payloadLen+ (4-1).U ) )
} }
} }
@@ -231,7 +229,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( io.axis.fire ){ when( io.axis.fire ){
axis_valid := false.B axis_valid := false.B
} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | (stateCurr === STATE_PAYLOAD & ~isReleaseLock) ) ){ } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
axis_valid := true.B axis_valid := true.B
} }

10
src/main/scala/backBoard/ebus/CDROut.scala
View File

@@ -35,7 +35,7 @@ class CDROut extends Module{
val bitCnt = Reg(UInt(4.W)) val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(7.W)) //payload 计数用于插入解锁位 val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val shiftData = RegInit(0.U(10.W)) val shiftData = RegInit(0.U(10.W))
@@ -47,7 +47,7 @@ class CDROut extends Module{
io.serDat := shiftData.extract(9) io.serDat := shiftData.extract(9)
io.axis.ready := io.axis.ready :=
bitCnt === 9.U & ~byteCnt.andR & ( bitCnt === 9.U & (
(stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) | (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
(stateCurr === STATE_PAYLOAD) (stateCurr === STATE_PAYLOAD)
) )
@@ -71,14 +71,10 @@ class CDROut extends Module{
( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata), ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
)) ))
} .elsewhen( stateCurr === STATE_PAYLOAD ){ } .elsewhen( stateCurr === STATE_PAYLOAD ){
when( byteCnt.andR ){//全1用于提示接收解锁
shiftData := "b0000000010".U
} .otherwise{
shiftData := Dualb4b5Encoder(io.axis.bits.tdata) shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
} }
} }
} }
}
when( stateCurr === STATE_IDLE ){ //PRE when( stateCurr === STATE_IDLE ){ //PRE
@@ -91,7 +87,7 @@ class CDROut extends Module{
} }
} }
when( (stateCurr === STATE_IDLE) ){ when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
byteCnt := 0.U byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){ } .elsewhen( bitCnt === 9.U ){
byteCnt := byteCnt + 1.U byteCnt := byteCnt + 1.U