From 0291d445ca69ce5f122985fcec819b14eda75f53 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 20 Aug 2025 15:40:25 +0800
Subject: [PATCH] =?UTF-8?q?Revert=20"cdrout=20=E6=AF=8F128byte=E5=8F=91?=
 =?UTF-8?q?=E9=80=81=E6=97=A0=E6=84=8F=E4=B9=89=E2=80=9Cb0000000010?=
 =?UTF-8?q?=E2=80=9D=E7=94=A8=E4=BA=8E=E8=A7=A3=E9=94=81cdrin=E5=B9=B6?=
 =?UTF-8?q?=E9=87=8D=E6=96=B0=E4=B8=8A=E9=94=81"?=
MIME-Version: 1.0
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This reverts commit d7146a786bf84fdbc0819b6a2b0e60dd0f5d19e5.
---
 src/main/scala/backBoard/ebus/CDRIn.scala  | 12 +++++-------
 src/main/scala/backBoard/ebus/CDROut.scala | 12 ++++--------
 2 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 8307909..7fe74d6 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -110,12 +110,12 @@ trait CDRInMultiSample{ this: CDRInBase =>
       (sampleReg_sync(i+0) & sampleReg_sync(i+1))
     }
 
-  val clearCnt = Reg(UInt(3.W))
+  val clearCnt = Reg(UInt(4.W))
   val arbLock = Reg(UInt( clkNum.W ))
   val isLock = RegInit(false.B)
 
   when( sampleReg.reduce(_|_) === false.B ){
-    when( clearCnt =/= 6.U ){
+    when( clearCnt =/= 10.U ){
       clearCnt := clearCnt + 1.U
     }
   } .otherwise{
@@ -132,7 +132,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
         isLock := true.B
       }
     }
-  } .elsewhen( clearCnt === 6.U ){
+  } .elsewhen( clearCnt === 10.U ){
     isLock := false.B
   }
 
@@ -171,7 +171,6 @@ trait CDRInAxis{ this: CDRInBase =>
   val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
 
   val shiftData = Dualb4b5Decoder(checkSFD(9,0))
-  val isReleaseLock = checkSFD(9,0) === "b0000000010".U
 
   val payloadLen = RegInit(0.U(12.W))
   when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
@@ -207,9 +206,8 @@ trait CDRInAxis{ this: CDRInBase =>
     when( stateCurr === STATE_HEADER ){
       byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
       assert( byteCnt <= (HeaderByte-1).U )
-      assert(~isReleaseLock)
     } .elsewhen( stateCurr === STATE_PAYLOAD ){
-      byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), Mux( isReleaseLock, byteCnt, byteCnt + 1.U ), 0.U )
+      byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
       assert( byteCnt <= ( payloadLen+ (4-1).U ) )
     }
   }
@@ -231,7 +229,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
   when( io.axis.fire ){
     axis_valid := false.B
-  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | (stateCurr === STATE_PAYLOAD & ~isReleaseLock) )  ){
+  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
     axis_valid := true.B
   }
 
diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 6dfb5c6..48d8cf9 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -35,7 +35,7 @@ class CDROut extends Module{
 
 
   val bitCnt = Reg(UInt(4.W))
-  val byteCnt = Reg(UInt(7.W)) //payload 计数用于插入解锁位
+  val byteCnt = Reg(UInt(3.W)) //payload dont need to count
 
   val shiftData = RegInit(0.U(10.W))
 
@@ -47,7 +47,7 @@ class CDROut extends Module{
 
   io.serDat := shiftData.extract(9)
   io.axis.ready :=
-    bitCnt === 9.U & ~byteCnt.andR & (
+    bitCnt === 9.U & (
       (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
       (stateCurr === STATE_PAYLOAD)
     )
@@ -71,11 +71,7 @@ class CDROut extends Module{
           ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
         ))
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
-        when( byteCnt.andR ){//全1用于提示接收解锁
-          shiftData := "b0000000010".U
-        } .otherwise{
-          shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
-        }
+        shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
       }
     }
   }
@@ -91,7 +87,7 @@ class CDROut extends Module{
     }
   }
 
-  when( (stateCurr === STATE_IDLE) ){
+  when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
     byteCnt := 0.U
   } .elsewhen( bitCnt === 9.U ){
     byteCnt := byteCnt + 1.U