rx DMA编译完成

2023-10-20 14:42:15 +08:00
parent c5f9b4d74f
commit 0215add0d4
8 changed files with 63 additions and 56 deletions
--- a/src/main/scala/Switch/mac/MacTilelink.scala
+++ b/src/main/scala/Switch/mac/MacTilelink.scala
@@ -57,7 +57,7 @@ abstract class MacTileLinkBase() extends Module{


    val rxEnq = new Receive_Enq_Bundle
-    val txDeq = Flipped(new Transmit_Deq_Bundle)
+    val txDeq = Flipped(new Transmit_Bundle)

  }

@@ -164,7 +164,7 @@ abstract class MacTileLinkBase() extends Module{


  val txRespValid = RegInit(false.B)
-  val txRespBits  = Reg(new Transmit_Deq_Resp_Bundle)
+  val txRespBits  = Reg(new Transmit_Resp_Bundle)

  io.txDeq.resp.valid := txRespValid
  io.txDeq.resp.bits  := txRespBits