rx DMA编译完成

2023-10-20 14:42:15 +08:00
parent c5f9b4d74f
commit 0215add0d4
8 changed files with 63 additions and 56 deletions
--- a/src/main/scala/Switch/WithSwitch.scala
+++ b/src/main/scala/Switch/WithSwitch.scala
@@ -12,7 +12,7 @@ trait WithSwitchMix { this: BaseSubsystem =>

    val switch = LazyModule(new Switch)

-    // sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch0.tlClientNode }
+    sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch.tlClientNode }
    // pbus.coupleTo("switch_cfg")   { switch0.tlMasterNode := TLFragmenter(pbus) := _ }
    pbus.coupleTo("switch_cfg")   { switch.ethReg.configNode   := TLFragmenter(pbus) := _ }