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rx DMA编译完成

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RuigeLee
2023-10-20 14:42:15 +08:00
parent c5f9b4d74f
commit 0215add0d4
8 changed files with 63 additions and 56 deletions
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11
src/main/scala/Switch/Switch.scala
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@@ -56,18 +56,23 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
outer.ethReg.module.io.asyncReset := io.asyncReset
outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
val switchMux = Module(new SwitchMux)
val switchMux = Module(new SwitchMux(dma_edge))
switchMux.io.rxEnq(0) <> mac(0).io.rxEnq
switchMux.io.txDeq(0) <> mac(0).io.txDeq
switchMux.io.triTx := outer.ethReg.module.io.triTx
switchMux.io.dmaMst.D.bits := dma_bus.d.bits
switchMux.io.dmaMst.D.valid := dma_bus.d.valid
dma_bus.d.ready := switchMux.io.dmaMst.D.ready
dma_bus.a.valid := switchMux.io.dmaMst.A.valid
dma_bus.a.bits := switchMux.io.dmaMst.A.bits
switchMux.io.dmaMst.A.ready := dma_bus.a.ready