ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rx DMA编译完成

Browse Source
This commit is contained in:
RuigeLee
2023-10-20 14:42:15 +08:00
parent c5f9b4d74f
commit 0215add0d4
8 changed files with 63 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/Switch/MacRegisters.scala
View File

@@ -324,8 +324,8 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
)),
( 30 << 2 ) ->
RegFieldGroup("BD", Some("bd"),
RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ),Some(RegFieldDesc("bd", "bd", reset=Some(0x0)))) ++ Seq(
RegFieldGroup("BD", Some("bd"), Seq(
RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", "bd", reset=Some(0x0)))
)),
)