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寄存器空间换dp-sram完成

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This commit is contained in:
RuigeLee
2024-03-28 15:09:48 +08:00
parent eb47b3e94d
commit 00fb93f47b
2 changed files with 127 additions and 57 deletions
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111
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -47,6 +47,10 @@ class BackBoardMstBase extends Module{ //10M
mirrorReg.io.addrB := DontCare mirrorReg.io.addrB := DontCare
mirrorReg.io.datawB := DontCare mirrorReg.io.datawB := DontCare
mirrorReg.io.enwB := false.B mirrorReg.io.enwB := false.B
mirrorReg.io.enrB := false.B
assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) )
assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )
// val statusCDRErr = RegInit( false.B ) // val statusCDRErr = RegInit( false.B )
// val statusCRCErr = RegInit( false.B ) // val statusCRCErr = RegInit( false.B )
@@ -133,7 +137,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
mirrorReg.io.addrA := activeAddr mirrorReg.io.addrA := activeAddr
mirrorReg.io.datawA := io.FSMC.ADIn mirrorReg.io.datawA := io.FSMC.ADIn
mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
// mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar) io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)
@@ -171,18 +175,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
} }
//10M //10M
when(~RegNext( io.testIO, false.B ) & io.testIO){ val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B)
when(~testIOShift(0) & io.testIO){
mirrorReg.io.addrB := 1.U mirrorReg.io.addrB := 1.U
mirrorReg.io.datawB := DontCare mirrorReg.io.enrB := true.B
mirrorReg.io.enwB := false.B } .elsewhen( ~testIOShift(1) & testIOShift(0)){
when( mirrorReg.io.datarB === 0.U ){ when( mirrorReg.io.datarB === 0.U ){
ctrlInit := true.B ctrlInit := true.B
} }
when( mirrorReg.io.datarB === 1.U ){ when( mirrorReg.io.datarB === 1.U ){
ctrlSynch := true.B ctrlSynch := true.B
} }
@@ -269,29 +272,40 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
slave_type_num := 0.U slave_type_num := 0.U
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 0.U ){ //statusInit } .elsewhen( stateCur === 0.U ){
stateCur := 1.U stateCur := 1.U
// write statusInit
mirrorReg.io.addrB := 7.U mirrorReg.io.addrB := 7.U
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ } .elsewhen( stateCur === 1.U ){
stateCur := 2.U stateCur := 2.U
mirrorReg.io.addrB := 2.U //req slvnum
slvNum := mirrorReg.io.datarB mirrorReg.io.addrB := 2.U
mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 2.U ){ } .elsewhen( stateCur === 2.U ){
stateCur := 3.U stateCur := 3.U
//lock slvNum
slvNum := mirrorReg.io.datarB
//req slaveDataLength
mirrorReg.io.addrB := 6.U mirrorReg.io.addrB := 6.U
slaveDataLength := mirrorReg.io.datarB mirrorReg.io.enrB := true.B
} }
.elsewhen( stateCur === 3.U ){ .elsewhen( stateCur === 3.U ){
stateCur := 4.U stateCur := 4.U
//lock slaveDataLength
slaveDataLength := mirrorReg.io.datarB
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum ) slave_type_num := Cat( "b00".U(2.W), slvNum )
slaveDataLength := slaveDataLength // slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -306,15 +320,13 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
timeoutCnt := timeoutCnt + 1.U timeoutCnt := timeoutCnt + 1.U
when( lvdsMst.io.slave_link_num_valid ){ when( lvdsMst.io.slave_link_num_valid ){
stateCur := 6.U
//linkNum //linkNum
mirrorReg.io.addrB := 5.U mirrorReg.io.addrB := 5.U
mirrorReg.io.datawB := lvdsMst.io.slave_link_num mirrorReg.io.datawB := lvdsMst.io.slave_link_num
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
stateCur := 6.U
ctrlInit := false.B
interrupt := true.B
} }
when( timeoutCnt === 6000.U ){ when( timeoutCnt === 6000.U ){
@@ -325,19 +337,21 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
ctrlInit := false.B
interrupt := true.B
} }
} .elsewhen( stateCur === 6.U ){ //statusInit } .elsewhen( stateCur === 6.U ){
stateCur := 7.U stateCur := 7.U
//statusInit
mirrorReg.io.addrB := 7.U mirrorReg.io.addrB := 7.U
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
ctrlInit := false.B
interrupt := true.B
} .elsewhen( stateCur === 7.U ){ } .elsewhen( stateCur === 7.U ){
} }
@@ -360,22 +374,33 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
mirrorReg.io.addrB := 8.U mirrorReg.io.addrB := 8.U
mirrorReg.io.datawB := 0.U mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ //slvnum } .elsewhen( stateCur === 1.U ){
stateCur := 2.U stateCur := 2.U
//req slvnum
mirrorReg.io.addrB := 2.U mirrorReg.io.addrB := 2.U
slvNum := mirrorReg.io.datarB mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 2.U ){ //slaveDataLength } .elsewhen( stateCur === 2.U ){ //slaveDataLength
stateCur := 3.U stateCur := 3.U
//lock slvNum
slvNum := mirrorReg.io.datarB
mirrorReg.io.addrB := 6.U mirrorReg.io.addrB := 6.U
slaveDataLength := mirrorReg.io.datarB mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 3.U ){ } .elsewhen( stateCur === 3.U ){
stateCur := 4.U stateCur := 4.U
//lock slaveDataLength
slaveDataLength := mirrorReg.io.datarB
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b01".U(2.W), slvNum ) slave_type_num := Cat( "b01".U(2.W), slvNum )
slaveDataLength := slaveDataLength // slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -390,17 +415,16 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 6.U stateCur := 6.U
//statusSync
mirrorReg.io.addrB := 8.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlSynch := false.B ctrlSynch := false.B
interrupt := true.B interrupt := true.B
} }
} .elsewhen( stateCur === 6.U ){
stateCur := 7.U
mirrorReg.io.addrB := 8.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 7.U ){
} .otherwise{ } .otherwise{
} }
@@ -433,18 +457,26 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
stateCur := 2.U stateCur := 2.U
mirrorReg.io.addrB := 2.U mirrorReg.io.addrB := 2.U
slvNum := mirrorReg.io.datarB mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 2.U ){ //slaveDataLength } .elsewhen( stateCur === 2.U ){ //slaveDataLength
stateCur := 3.U stateCur := 3.U
//lock slvNum
slvNum := mirrorReg.io.datarB
mirrorReg.io.addrB := 6.U mirrorReg.io.addrB := 6.U
slaveDataLength := mirrorReg.io.datarB mirrorReg.io.enrB := true.B
} .elsewhen( stateCur === 3.U ){ //setting } .elsewhen( stateCur === 3.U ){ //setting
stateCur := 4.U stateCur := 4.U
//lock slaveDataLength
slaveDataLength := mirrorReg.io.datarB
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b10".U(2.W), slvNum ) slave_type_num := Cat( "b10".U(2.W), slvNum )
slaveDataLength := slaveDataLength // slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 4.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
@@ -464,16 +496,19 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
} .elsewhen( stateCur === 6.U ){ } .elsewhen( stateCur === 6.U ){
when( lvdsMst.io.upstream_crc_valid ){ when( lvdsMst.io.upstream_crc_valid ){
stateCur := 7.U stateCur := 7.U
//statusTransmit
mirrorReg.io.addrB := 9.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlTransmit := false.B ctrlTransmit := false.B
interrupt := true.B interrupt := true.B
} }
} .elsewhen( stateCur === 7.U ){ //statusTransmit } .elsewhen( stateCur === 7.U ){
stateCur := 8.U // stateCur := 8.U
mirrorReg.io.addrB := 9.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 8.U ){
} .otherwise{ } .otherwise{
} }

71
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -248,6 +248,7 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
val datawA = Input( UInt(16.W) ) val datawA = Input( UInt(16.W) )
val datarA = Output( UInt(16.W) ) val datarA = Output( UInt(16.W) )
val enwA = Input(Bool()) val enwA = Input(Bool())
val enrA = Input(Bool())
val clockA = Input(Bool()) val clockA = Input(Bool())
@@ -255,6 +256,7 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
val datawB = Input( UInt(16.W) ) val datawB = Input( UInt(16.W) )
val datarB = Output( UInt(16.W) ) val datarB = Output( UInt(16.W) )
val enwB = Input(Bool()) val enwB = Input(Bool())
val enrB = Input(Bool())
val clockB = Input(Bool()) val clockB = Input(Bool())
} }
@@ -266,34 +268,67 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
| input [15:0] datawA, | input [15:0] datawA,
| input [9:0] addrA, | input [9:0] addrA,
| input enwA, | input enwA,
| input enrA,
| output [15:0] datarA, | output [15:0] datarA,
| input clockA, | input clockA,
| |
| input [15:0] datawB, | input [15:0] datawB,
| input [9:0] addrB, | input [9:0] addrB,
| input enwB, | input enwB,
| input enrB,
| output [15:0] datarB, | output [15:0] datarB,
| input clockB | input clockB
| ); | );
| |
| Gowin_DPB your_instance_name( | reg [15:0] mem[0:1023];
| .douta(datarA), //output [15:0] douta | reg [15:0] data_outa_reg = 16'b0;
| .doutb(datarB), //output [15:0] doutb | reg [15:0] data_outb_reg = 16'b0;
| .clka(clockA), //input clka |
| .ocea(1'b1), //input ocea | assign datarA = data_outa_reg;
| .cea(1'b1), //input cea | assign datarB = data_outb_reg;
| .reseta(1'b0), //input reseta |
| .wrea(enwA), //input wrea | always@( posedge clockA ) begin
| .clkb(clockB), //input clkb | if( enrA ) begin
| .oceb(1'b1), //input oceb | end
| .ceb(1'b1), //input ceb |
| .resetb(1'b0), //input resetb | if( enwA ) begin
| .wreb(enwB), //input wreb | mem[addrA] <= datawA;
| .ada(addrA), //input [3:0] ada | end else begin
| .dina(datawA), //input [15:0] dina | data_outa_reg <= mem[addrA];
| .adb(addrB), //input [3:0] adb | end
| .dinb(datawB) //input [15:0] dinb | end
| ); |
|
| always@( posedge clockB ) begin
| if(enrB) begin
| end
|
| if( enwB ) begin
| mem[addrB] <= datawB;
| end else begin
| data_outb_reg <= mem[addrB];
| end
| end
|
|
| //Gowin_DPB your_instance_name(
| // .douta(datarA), //output [15:0] douta
| // .doutb(datarB), //output [15:0] doutb
| // .clka(clockA), //input clka
| // .ocea(1'b1), //input ocea
| // .cea(1'b1), //input cea
| // .reseta(1'b0), //input reseta
| // .wrea(enwA), //input wrea
| // .clkb(clockB), //input clkb
| // .oceb(1'b1), //input oceb
| // .ceb(1'b1), //input ceb
| // .resetb(1'b0), //input resetb
| // .wreb(enwB), //input wreb
| // .ada(addrA), //input [3:0] ada
| // .dina(datawA), //input [15:0] dina
| // .adb(addrB), //input [3:0] adb
| // .dinb(datawB) //input [15:0] dinb
| //);
| |
|endmodule |endmodule
""".stripMargin) """.stripMargin)