diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index c5f7cbd..ab14892 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -47,6 +47,10 @@ class BackBoardMstBase extends Module{ //10M
     mirrorReg.io.addrB  := DontCare
     mirrorReg.io.datawB := DontCare
     mirrorReg.io.enwB   := false.B
+    mirrorReg.io.enrB   := false.B
+
+    assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) )
+    assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )
 
   // val statusCDRErr  = RegInit( false.B )
   // val statusCRCErr  = RegInit( false.B )
@@ -133,7 +137,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     mirrorReg.io.addrA  := activeAddr
     mirrorReg.io.datawA := io.FSMC.ADIn
     mirrorReg.io.enwA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
-    // mirrorReg.io.enrA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
+    mirrorReg.io.enrA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
 
     io.FSMC.ADOut   := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)
 
@@ -171,18 +175,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   }
 
   //10M
-  when(~RegNext( io.testIO, false.B ) & io.testIO){
+  val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B)
+  when(~testIOShift(0) & io.testIO){
 
     mirrorReg.io.addrB  := 1.U
-    mirrorReg.io.datawB := DontCare
-    mirrorReg.io.enwB   := false.B
-
+    mirrorReg.io.enrB   := true.B
+  } .elsewhen( ~testIOShift(1) & testIOShift(0)){
     when( mirrorReg.io.datarB === 0.U ){
       ctrlInit   := true.B
     }
 
     when( mirrorReg.io.datarB === 1.U ){
-      
       ctrlSynch   := true.B
     }
 
@@ -269,29 +272,40 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       slave_type_num       := 0.U
       tx_start := false.B
       
-    } .elsewhen( stateCur === 0.U ){ //statusInit 
+    } .elsewhen( stateCur === 0.U ){
       stateCur := 1.U
 
+      // write statusInit
       mirrorReg.io.addrB  := 7.U
       mirrorReg.io.datawB := 0.U
       mirrorReg.io.enwB   := true.B
     } .elsewhen( stateCur === 1.U ){
       stateCur := 2.U
 
-      mirrorReg.io.addrB  := 2.U
-      slvNum := mirrorReg.io.datarB
+      //req slvnum
+      mirrorReg.io.addrB := 2.U
+      mirrorReg.io.enrB  := true.B
+
     } .elsewhen( stateCur === 2.U ){
       stateCur := 3.U
 
+      //lock slvNum
+      slvNum := mirrorReg.io.datarB
+
+      //req slaveDataLength
       mirrorReg.io.addrB  := 6.U
-      slaveDataLength := mirrorReg.io.datarB
+      mirrorReg.io.enrB  := true.B
+
     }
     .elsewhen( stateCur === 3.U ){
       stateCur := 4.U
 
+      //lock slaveDataLength
+      slaveDataLength := mirrorReg.io.datarB
+
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b00".U(2.W), slvNum )
-      slaveDataLength      := slaveDataLength
+      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -306,15 +320,13 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       timeoutCnt := timeoutCnt + 1.U
 
       when( lvdsMst.io.slave_link_num_valid ){
+        stateCur := 6.U
+
         //linkNum 
         mirrorReg.io.addrB  := 5.U
         mirrorReg.io.datawB := lvdsMst.io.slave_link_num
         mirrorReg.io.enwB   := true.B
 
-
-        stateCur := 6.U
-        ctrlInit    := false.B
-        interrupt   := true.B
       }
 
       when( timeoutCnt === 6000.U ){
@@ -325,19 +337,21 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
         mirrorReg.io.datawB := 0.U
         mirrorReg.io.enwB   := true.B
 
-        ctrlInit    := false.B
-        interrupt   := true.B
       }
 
 
 
-    } .elsewhen( stateCur === 6.U ){ //statusInit 
+    } .elsewhen( stateCur === 6.U ){ 
       stateCur := 7.U
 
+      //statusInit 
       mirrorReg.io.addrB  := 7.U
       mirrorReg.io.datawB := 1.U
       mirrorReg.io.enwB   := true.B
 
+      ctrlInit    := false.B
+      interrupt   := true.B
+
     } .elsewhen( stateCur === 7.U ){
 
     }
@@ -360,22 +374,33 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
       mirrorReg.io.addrB  := 8.U
       mirrorReg.io.datawB := 0.U
       mirrorReg.io.enwB   := true.B
-    } .elsewhen( stateCur === 1.U ){ //slvnum
+    } .elsewhen( stateCur === 1.U ){ 
       stateCur := 2.U
 
+      //req slvnum
       mirrorReg.io.addrB  := 2.U
-      slvNum := mirrorReg.io.datarB
+      mirrorReg.io.enrB   := true.B
+
+
     } .elsewhen( stateCur === 2.U ){ //slaveDataLength
       stateCur := 3.U
 
+      //lock slvNum
+      slvNum := mirrorReg.io.datarB
+
       mirrorReg.io.addrB  := 6.U
-      slaveDataLength := mirrorReg.io.datarB
+      mirrorReg.io.enrB   := true.B
+
+
     } .elsewhen( stateCur === 3.U ){
       stateCur := 4.U
 
+      //lock slaveDataLength
+      slaveDataLength := mirrorReg.io.datarB
+
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b01".U(2.W), slvNum )
-      slaveDataLength      := slaveDataLength
+      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -390,17 +415,16 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
 
       when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
         stateCur := 6.U
+
+        //statusSync
+        mirrorReg.io.addrB  := 8.U
+        mirrorReg.io.datawB := 1.U
+        mirrorReg.io.enwB   := true.B
+
         ctrlSynch   := false.B
         interrupt   := true.B
       }
 
-    } .elsewhen( stateCur === 6.U ){
-      stateCur := 7.U
-      mirrorReg.io.addrB  := 8.U
-      mirrorReg.io.datawB := 1.U
-      mirrorReg.io.enwB   := true.B
-    } .elsewhen( stateCur === 7.U ){
-
     } .otherwise{
 
     }
@@ -433,18 +457,26 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
       stateCur := 2.U
 
       mirrorReg.io.addrB  := 2.U
-      slvNum := mirrorReg.io.datarB
+      mirrorReg.io.enrB   := true.B
+
     } .elsewhen( stateCur === 2.U ){ //slaveDataLength
       stateCur := 3.U
 
+      //lock slvNum
+      slvNum := mirrorReg.io.datarB
+
       mirrorReg.io.addrB  := 6.U
-      slaveDataLength := mirrorReg.io.datarB
+      mirrorReg.io.enrB   := true.B
+
     } .elsewhen( stateCur === 3.U  ){ //setting
       stateCur := 4.U
 
+      //lock slaveDataLength
+      slaveDataLength := mirrorReg.io.datarB
+
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b10".U(2.W), slvNum )
-      slaveDataLength      := slaveDataLength
+      // slaveDataLength      := slaveDataLength
 
       tx_start := false.B
     } .elsewhen( stateCur === 4.U ){ // tx start
@@ -464,16 +496,19 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
     } .elsewhen( stateCur === 6.U ){
       when( lvdsMst.io.upstream_crc_valid ){
         stateCur := 7.U
+
+        //statusTransmit
+        mirrorReg.io.addrB  := 9.U
+        mirrorReg.io.datawB := 1.U
+        mirrorReg.io.enwB   := true.B
+
         ctrlTransmit := false.B
         interrupt    := true.B
       }
 
-    } .elsewhen( stateCur === 7.U ){  //statusTransmit
-      stateCur := 8.U
-      mirrorReg.io.addrB  := 9.U
-      mirrorReg.io.datawB := 1.U
-      mirrorReg.io.enwB   := true.B
-    } .elsewhen( stateCur === 8.U ){
+    } .elsewhen( stateCur === 7.U ){  
+      // stateCur := 8.U
+
     } .otherwise{
 
     }
diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala
index ad4ebe3..822604e 100644
--- a/src/main/scala/backBoard/MirrorSRAM.scala
+++ b/src/main/scala/backBoard/MirrorSRAM.scala
@@ -248,6 +248,7 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
       val datawA  = Input( UInt(16.W) )
       val datarA  = Output( UInt(16.W) )
       val enwA    = Input(Bool())
+      val enrA    = Input(Bool())
       val clockA  = Input(Bool())
 
 
@@ -255,6 +256,7 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
       val datawB = Input( UInt(16.W) )
       val datarB = Output( UInt(16.W) )
       val enwB   = Input(Bool())
+      val enrB   = Input(Bool())
       val clockB = Input(Bool())
 
   }
@@ -266,34 +268,67 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
       |  	input [15:0]  datawA,
       |  	input [9:0]   addrA,
       |  	input enwA,
+      |  	input enrA,
       |  	output [15:0] datarA,
       |  	input clockA,
       |
       |  	input [15:0]  datawB,
       |  	input [9:0]   addrB,
-      |  	input enwB,    
+      |  	input enwB,
+      |  	input enrB,
       |  	output [15:0] datarB,
       |  	input clockB
       |  );
       |  
-      |  Gowin_DPB your_instance_name(
-      |    .douta(datarA), //output [15:0] douta
-      |    .doutb(datarB), //output [15:0] doutb
-      |    .clka(clockA), //input clka
-      |    .ocea(1'b1), //input ocea
-      |    .cea(1'b1), //input cea
-      |    .reseta(1'b0), //input reseta
-      |    .wrea(enwA), //input wrea
-      |    .clkb(clockB), //input clkb
-      |    .oceb(1'b1), //input oceb
-      |    .ceb(1'b1), //input ceb
-      |    .resetb(1'b0), //input resetb
-      |    .wreb(enwB), //input wreb
-      |    .ada(addrA), //input [3:0] ada
-      |    .dina(datawA), //input [15:0] dina
-      |    .adb(addrB), //input [3:0] adb
-      |    .dinb(datawB) //input [15:0] dinb
-      |  );
+      |  reg [15:0] mem[0:1023];
+      |  reg [15:0] data_outa_reg = 16'b0;
+      |  reg [15:0] data_outb_reg = 16'b0;
+      |
+      |  assign datarA = data_outa_reg;
+      |  assign datarB = data_outb_reg;
+      |
+      |  always@( posedge clockA ) begin
+      |    if( enrA ) begin
+      |    end
+      |
+      |    if( enwA ) begin
+      |      mem[addrA] <= datawA;
+      |    end else begin
+      |      data_outa_reg <= mem[addrA];
+      |    end
+      |  end
+      |
+      |
+      |  always@( posedge clockB ) begin
+      |    if(enrB) begin
+      |    end
+      |
+      |    if( enwB ) begin
+      |      mem[addrB] <= datawB;
+      |    end else begin
+      |      data_outb_reg <= mem[addrB];
+      |    end
+      |  end
+      |
+      |
+      |  //Gowin_DPB your_instance_name(
+      |  //  .douta(datarA), //output [15:0] douta
+      |  //  .doutb(datarB), //output [15:0] doutb
+      |  //  .clka(clockA), //input clka
+      |  //  .ocea(1'b1), //input ocea
+      |  //  .cea(1'b1), //input cea
+      |  //  .reseta(1'b0), //input reseta
+      |  //  .wrea(enwA), //input wrea
+      |  //  .clkb(clockB), //input clkb
+      |  //  .oceb(1'b1), //input oceb
+      |  //  .ceb(1'b1), //input ceb
+      |  //  .resetb(1'b0), //input resetb
+      |  //  .wreb(enwB), //input wreb
+      |  //  .ada(addrA), //input [3:0] ada
+      |  //  .dina(datawA), //input [15:0] dina
+      |  //  .adb(addrB), //input [3:0] adb
+      |  //  .dinb(datawB) //input [15:0] dinb
+      |  //);
       |
       |endmodule
     """.stripMargin)