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寄存器空间换dp-sram完成

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RuigeLee
2024-03-28 15:09:48 +08:00
parent eb47b3e94d
commit 00fb93f47b
2 changed files with 127 additions and 57 deletions
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73
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -248,6 +248,7 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
val datawA = Input( UInt(16.W) )
val datarA = Output( UInt(16.W) )
val enwA = Input(Bool())
val enrA = Input(Bool())
val clockA = Input(Bool())
@@ -255,6 +256,7 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
val datawB = Input( UInt(16.W) )
val datarB = Output( UInt(16.W) )
val enwB = Input(Bool())
val enrB = Input(Bool())
val clockB = Input(Bool())
}
@@ -266,34 +268,67 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
| input [15:0] datawA,
| input [9:0] addrA,
| input enwA,
| input enrA,
| output [15:0] datarA,
| input clockA,
|
| input [15:0] datawB,
| input [9:0] addrB,
| input enwB,
| input enwB,
| input enrB,
| output [15:0] datarB,
| input clockB
| );
|
| Gowin_DPB your_instance_name(
| .douta(datarA), //output [15:0] douta
| .doutb(datarB), //output [15:0] doutb
| .clka(clockA), //input clka
| .ocea(1'b1), //input ocea
| .cea(1'b1), //input cea
| .reseta(1'b0), //input reseta
| .wrea(enwA), //input wrea
| .clkb(clockB), //input clkb
| .oceb(1'b1), //input oceb
| .ceb(1'b1), //input ceb
| .resetb(1'b0), //input resetb
| .wreb(enwB), //input wreb
| .ada(addrA), //input [3:0] ada
| .dina(datawA), //input [15:0] dina
| .adb(addrB), //input [3:0] adb
| .dinb(datawB) //input [15:0] dinb
| );
| reg [15:0] mem[0:1023];
| reg [15:0] data_outa_reg = 16'b0;
| reg [15:0] data_outb_reg = 16'b0;
|
| assign datarA = data_outa_reg;
| assign datarB = data_outb_reg;
|
| always@( posedge clockA ) begin
| if( enrA ) begin
| end
|
| if( enwA ) begin
| mem[addrA] <= datawA;
| end else begin
| data_outa_reg <= mem[addrA];
| end
| end
|
|
| always@( posedge clockB ) begin
| if(enrB) begin
| end
|
| if( enwB ) begin
| mem[addrB] <= datawB;
| end else begin
| data_outb_reg <= mem[addrB];
| end
| end
|
|
| //Gowin_DPB your_instance_name(
| // .douta(datarA), //output [15:0] douta
| // .doutb(datarB), //output [15:0] doutb
| // .clka(clockA), //input clka
| // .ocea(1'b1), //input ocea
| // .cea(1'b1), //input cea
| // .reseta(1'b0), //input reseta
| // .wrea(enwA), //input wrea
| // .clkb(clockB), //input clkb
| // .oceb(1'b1), //input oceb
| // .ceb(1'b1), //input ceb
| // .resetb(1'b0), //input resetb
| // .wreb(enwB), //input wreb
| // .ada(addrA), //input [3:0] ada
| // .dina(datawA), //input [15:0] dina
| // .adb(addrB), //input [3:0] adb
| // .dinb(datawB) //input [15:0] dinb
| //);
|
|endmodule
""".stripMargin)