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基本功能单元编译通过，开始搭建测试环境校对流水线

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This commit is contained in:
Ruige Lee
2025-04-11 17:57:47 +08:00
parent dabfc86983
commit 00a7b0fe6e
10 changed files with 493 additions and 259 deletions
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47
src/main/scala/backBoard/shin/SlaveSendGen.scala
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@@ -10,30 +10,48 @@ class SubMsgTxInfo extends SubMsgHeader{
class SlaveSendGenIO extends Bundle{
val data = for( 0 until 2 ) yield { Flipped( Decoupled(UInt(8.W)) ) }
val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) )
val frameReq = Flipped(Decoupled( new FrameHeader ))
val subMsgReq = Flipped(Decoupled( new SubMsgHeader ))
val subMsgReq = Flipped(Decoupled( new SubMsgTxInfo ))
val send = Decoupled(new AXIS_Bundle(8))
val isError = Output(Bool())
}
class SlaveSendGen extends Module{
val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
val crc = Module(new crc32_8)
val STATE_IDLE = 0.U //空闲
val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_SUBMSG_HEADER = 2.U
val STATE_SUBMSG_DATA = 3.U
val STATE_CRC = 4.U //CRC校验
val STATE_ERROR = 5.U
// val STATE_WAIT = 6.U
val stateNext = Wire(UInt(3.W))
val stateCurr = RegNext(stateNext, STATE_IDLE)
io.isError := stateCurr === STATE_ERROR
crc.io.isEnable :=
stateCurr === STATE_FRAME_HEADER |
stateCurr === STATE_SUBMSG_HEADER |
stateCurr === STATE_SUBMSG_DATA
crc.io.dataIn := tdata_submsg_data
crc.reset := reset.asBool | stateCurr === STATE_IDLE
@@ -41,7 +59,7 @@ class SlaveSendGen extends Module{
val frameInfo = Reg(new FrameHeader)
val subMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val subMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
val isPingFill = RegInit(false.B)
val isPingEmit = RegInit(false.B)
@@ -59,6 +77,9 @@ class SlaveSendGen extends Module{
}
}
io.frameReq.ready := true.B
io.subMsgReq.ready := true.B
val lengthCnt = Reg(UInt(12.W))
val frameLenCnt = Reg(UInt(12.W))
@@ -82,25 +103,15 @@ class SlaveSendGen extends Module{
val STATE_IDLE = 0.U //空闲
val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_SUBMSG_HEADER = 2.U
val STATE_SUBMSG_DATA = 3.U
val STATE_CRC = 4.U //CRC校验
val STATE_ERROR = 5.U
// val STATE_WAIT = 6.U
val stateNext = Wire(UInt(3.W))
val stateCurr = RegNext(stateNext, STATE_IDLE(3.W))
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
(stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER),
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (64-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER),
(stateCurr === STATE_SUBMSG_DATA) ->
Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文
Mux( frameLenCnt === frameInfo.lengthCnt, STATE_CRC, //主报文长度达到， 进CRC
Mux( frameLenCnt === frameInfo.frameLenAim, STATE_CRC, //主报文长度达到， 进CRC
Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文
STATE_SUBMSG_DATA
),
@@ -122,8 +133,8 @@ class SlaveSendGen extends Module{
val tdata_frame_header = Mux1H(Seq(
(lengthCnt === 0.U) -> frameLenAim(11,4),
(lengthCnt === 1.U) -> Cat( frameLenAim(3,0), 0.U(2.W), frameStyle),
(lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4),
(lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle),
))
val tdata_submsg_header = Mux1H(Seq(
@@ -142,7 +153,7 @@ class SlaveSendGen extends Module{
(subMsgInfoSel.source === 1.U) -> io.data(1).bits,
))
crc.io.dataIn := tdata_submsg_data
val tdata_crc = Mux1H(Seq(