diff --git a/Makefile b/Makefile index ad42021..f16f15b 100644 --- a/Makefile +++ b/Makefile @@ -36,6 +36,17 @@ back: cp ./src/main/verilog/spi_top.v ./generated/back/ cp ./src/main/verilog/defineParam.v ./generated/back/ +shin: + rm -f ./generated/shin/* + sbt "test:runMain test.testShinModule" + +testShin: + iverilog -Wall \ + -o ./tb/build/shinTest.iverilog \ + -y ./generated/shin \ + -I ./generated/shin \ + ./tb/shinTest/SlaveParserTb.v + vvp.exe -N ./build/shinTest.iverilog -lxt2 ef: sbt "test:runMain test.testModule" diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 527ede7..ecf9b12 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -1,19 +1,19 @@ -package BACK +// package BACK -import chisel3._ -import chisel3.util._ +// import chisel3._ +// import chisel3.util._ -class InterfaceIO extends Module{ +// class InterfaceIO extends Module{ -} +// } -abstract class InterfaceBase extends Module{ - val io: InterfaceIO = IO(new InterfaceIO) +// abstract class InterfaceBase extends Module{ +// val io: InterfaceIO = IO(new InterfaceIO) -} +// } -class Interface extends InterfaceBase{ +// class Interface extends InterfaceBase{ -} \ No newline at end of file +// } \ No newline at end of file diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index 6f6e91e..67570ca 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -1,19 +1,19 @@ -package BACK +// package BACK -import chisel3._ -import chisel3.util._ +// import chisel3._ +// import chisel3.util._ -class MasterParserIO extends Module{ +// class MasterParserIO extends Module{ -} +// } -abstract class MasterParserBase extends Module{ - val io: MasterParserIO = IO(new MasterParserIO) +// abstract class MasterParserBase extends Module{ +// val io: MasterParserIO = IO(new MasterParserIO) -} +// } -class MasterParser extends MasterParserBase{ +// class MasterParser extends MasterParserBase{ -} \ No newline at end of file +// } \ No newline at end of file diff --git a/src/main/scala/backBoard/shin/ShareSRAM.scala b/src/main/scala/backBoard/shin/ShareSRAM.scala index 8eb9054..b1c91f0 100644 --- a/src/main/scala/backBoard/shin/ShareSRAM.scala +++ b/src/main/scala/backBoard/shin/ShareSRAM.scala @@ -24,11 +24,11 @@ class ShareSRAMDP extends BlackBox with HasBlackBoxInline { val clockB = Input(Bool()) } - val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO) + val io: ShareSRAMDPIO = IO(new ShareSRAMDPIO) - setInline("MirrorSRAMDP.v", + setInline("ShareSRAMDP.v", """ - | module MirrorSRAMDP( + | module ShareSRAMDP( | input [7:0] datawA, | input [14:0] addrA, | input enwA, diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 439732c..e2ec179 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -1,54 +1,54 @@ -package BACK +// package BACK -import chisel3._ -import chisel3.util._ +// import chisel3._ +// import chisel3.util._ -class ShinTopIO extends Bundle{ - val clk8x = Input(Bool()) - val modeSel = Input(Bool())\ +// class ShinTopIO extends Bundle{ +// val clk8x = Input(Bool()) +// val modeSel = Input(Bool())\ - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) +// val dDatIn = Input(Bool()) +// val dDatOut = Output(Bool()) +// val uDatIn = Input(Bool()) +// val uDatOut = Output(Bool()) - val qspi = - val interrupt = Output(Bool()) - val ctrl = Input(UInt(4.W)) -} +// val qspi = +// val interrupt = Output(Bool()) +// val ctrl = Input(UInt(4.W)) +// } -class ShinTop extends Module{ - val io: ShinTopIO = IO(new ShinTopIO) +// class ShinTop extends Module{ +// val io: ShinTopIO = IO(new ShinTopIO) - val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } - val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } +// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } +// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } - val slaveParser = Module(new SlaveParser ) - val masterParser = Module(new MasterParser) +// val slaveParser = Module(new SlaveParser ) +// val masterParser = Module(new MasterParser) - val sram = Module(new ShareSRAMDP) +// val sram = Module(new ShareSRAMDP) - val interface = Module(new Interface) +// val interface = Module(new Interface) - sram.io.addrA := Input(UInt(15.W)) - sram.io.datawA := Input( UInt(8.W) ) - sram.io.datarA := Output( UInt(8.W) ) - sram.io.enwA := Input(Bool()) - sram.io.enrA := Input(Bool()) - sram.io.clockA := Input(Bool()) +// sram.io.addrA := Input(UInt(15.W)) +// sram.io.datawA := Input( UInt(8.W) ) +// sram.io.datarA := Output( UInt(8.W) ) +// sram.io.enwA := Input(Bool()) +// sram.io.enrA := Input(Bool()) +// sram.io.clockA := Input(Bool()) - sram.io.addrB := Input(UInt(15.W)) - sram.io.datawB := Input( UInt(8.W) ) - sram.io.datarB := Output( UInt(8.W) ) - sram.io.enwB := Input(Bool()) - sram.io.enrB := Input(Bool()) - sram.io.clockB := Input(Bool()) +// sram.io.addrB := Input(UInt(15.W)) +// sram.io.datawB := Input( UInt(8.W) ) +// sram.io.datarB := Output( UInt(8.W) ) +// sram.io.enwB := Input(Bool()) +// sram.io.enrB := Input(Bool()) +// sram.io.clockB := Input(Bool()) -} +// } diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index e70b4fc..8dba817 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -30,20 +30,33 @@ class ShareSRAMIO extends Bundle{ -class SlaveParserIO extends Module{ +class SlaveParserIO extends Bundle{ val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) ) val downOut = Decoupled(new AXIS_Bundle(8)) val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) ) val upOut = Decoupled(new AXIS_Bundle(8)) - val sram_r = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) } - val sram_w = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) } + val sram_r = Flipped(new ShareSRAMIO) + val sram_w = Flipped(new ShareSRAMIO) } abstract class SlaveParserBase extends Module{ val io: SlaveParserIO = IO(new SlaveParserIO) + val FRAME_STYLE_COMMON = 0.U + val FRAME_STYLE_PROBE = 1.U + + val STATE_IDLE = 0.U //空闲 + val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型 + val STATE_PAYLOAD_ADDR = 3.U //子报文地址 + val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度 + val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数 + val STATE_PAYLOAD_DATA = 6.U //子报文数据 + val STATE_CRC = 7.U //CRC校验 + val STATE_ERROR = 8.U // + val STATE_WAIT = 9.U @@ -54,96 +67,92 @@ abstract class SlaveParserBase extends Module{ val upSendGen = Module(new SlaveSendGen) - val devIndex = Reg(UInt(14.W)) //当前设备索引 + val localDevIndex = Reg(UInt(14.W)) //当前设备索引 // 认为只有下行到下行，上行到上行模式，探针是独立发起操作 // val downSinkSel = Reg(Bool()) // val upSinkSel = Reg(Bool()) - val downFrameInfo = Reg(new FrameHeader) - val downSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) } + val downFrameInfo = Reg(new FrameHeader) //下行大包头 - val upFrameInfo = Reg(new FrameHeader) - val upSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) } + val upFrameInfo = Reg(new FrameHeader) //上行大包头 - val isDownSendBusy = downRecParser.io.frameReq.ready - val isUpSendBusy = upRecParser.io.frameReq.ready + val isDownSendBusy = downSendGen.io.frameReq.ready + val isUpSendBusy = upSendGen.io.frameReq.ready val isDownSendPend = RegInit(false.B) val isUpSendPend = RegInit(false.B) - + // val isUpProbePending //处理主报文 + // when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包 + // // isUpSendPend := true.B //嗅探包不会立即发送，而是看门狗形式 + // //downFrameInfo := downRecParser.io.frameReq.bits + // } .elsewhen( ){ - //同时到来怎么办 - when( downRecParser.io.frameReq.fire ){ - when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包 - isUpSendPend := true.B - downFrameInfo := downRecParser.io.frameReq.bits - println("Warning! No busy protection!") - } .elsewhen( downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //下行来了一个普通包 - isDownSendPend := true.B - downFrameInfo := downRecParser.io.frameReq.bits - println("Warning! No busy protection!") - } - } .elsewhen( upRecParser.io.frameReq.fire ){ - when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包 - println("Probe Resp!") - } .elsewhen( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包 - isUpSendPend := true.B - upFrameInfo := upRecParser.io.frameReq.bits - println("Warning! No busy protection!") - } - } - - - val isDownSendProbe: Bool //下行探针 - val isUpSendProbe: Bool //上行探针 - val probeFrame: FrameHeader //固定化探针内容 - - downSendGen.io.frameReq.valid := - isDownSendPend | isDownSendProbe //下行转发 | 下行探针 - - assert( OneHot(isDownSendPend, isDownSendProbe) ) - - downSendGen.io.frameReq.bits := Mux1H(Seq( - isDownSendPend -> downFrameInfo, //下行转发 - isDownSendProbe -> probeFrame, //下行探针 - )) - when( downSendGen.io.frameReq.fire ){ isDownSendPend := false.B + } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包 + isDownSendPend := true.B + downFrameInfo := downRecParser.io.frameReq.bits } - upSendGen.io.frameReq.valid := - isUpSendPend | isUpSendProbe | //上行转发 | 上行探针 | 下行回环 - - assert( OneHot(isUpSendPend, isUpSendProbe) ) - - upSendGen.io.frameReq.bits := Mux1H(Seq( - isUpSendPend -> upFrameInfo, //上行转发 - isUpSendProbe -> probeFrame, //上行探针 - , //下行回环 - )) - + // when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包 + // println("Probe Resp!") when( upSendGen.io.frameReq.fire ){ isUpSendPend := false.B - } - - when( downSendGen.io.frameReq.fire ){ - isDownSendPend := false.B + } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包 + isUpSendPend := true.B + upFrameInfo := upRecParser.io.frameReq.bits } + // val isDownSendProbe: Bool //下行探针 + // val isUpSendProbe: Bool //上行探针 + // val probeFrame: FrameHeader //固定化探针内容 + + downSendGen.io.frameReq.valid := + isDownSendPend //| 下行转发 + //isDownSendProbe //下行探针 + + // assert( OneHot(isDownSendPend, isDownSendProbe) ) + + downSendGen.io.frameReq.bits := Mux1H(Seq( + isDownSendPend -> downFrameInfo, //下行转发 + //isDownSendProbe -> probeFrame, //下行探针 + )) + + + + + upSendGen.io.frameReq.valid := + isUpSendPend //| 上行转发 + //isUpSendProbe | // 上行探针 + + // assert( OneHot(isUpSendPend, isUpSendProbe) ) + + upSendGen.io.frameReq.bits := Mux1H(Seq( + isUpSendPend -> upFrameInfo, //上行转发 + //isUpSendProbe -> probeFrame, //上行探针 + )) + + + + + + + +//////////////////////////////////////// + //子报文 - val isDownSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isUpSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isUpSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } @@ -151,61 +160,50 @@ abstract class SlaveParserBase extends Module{ //接收子报文 - val downSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) } - val upSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) } + val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头 + val upSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } - val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } - val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } + val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } //子报文负载 + val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } - val isDownRecPing: Bool - val isUpRecPing: Bool + val isDownRecPing = RegInit(false.B) + val isUpRecPing = RegInit(false.B) //下行接收 when( downRecParser.io.subMsgReq.fire ){ when( isDownRecPing ){ - isDownSubMsgValid(0) := true.B - downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + downSubMsgInfo(0).workCnt := + Mux( + downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包 + (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作 + ), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt + ) + downSubMsgInfo(0).source := 0.U - //override 自身包 - when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ - when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U - } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo - } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U - } - } } .otherwise{ - isDownSubMsgValid(1) := true.B - downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + downSubMsgInfo(1).workCnt := + Mux( + downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包 + (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作 + ), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt + ) downSubMsgInfo(1).source := 1.U - //override 自身包 - when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ - when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U - } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo - } .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U - } - } } } @@ -216,20 +214,44 @@ abstract class SlaveParserBase extends Module{ downRecFifo(0).io.enq.valid := downRecParser.io.data.valid downRecFifo(0).io.enq.bits := downRecParser.io.data.bits downRecParser.io.data.ready := downRecFifo(0).io.enq.ready + + downRecFifo(1).io.enq.valid := false.B + downRecFifo(1).io.enq.bits := 0.U + } .otherwise{ + downRecFifo(0).io.enq.valid := false.B + downRecFifo(0).io.enq.bits := 0.U + downRecFifo(1).io.enq.valid := downRecParser.io.data.valid downRecFifo(1).io.enq.bits := downRecParser.io.data.bits downRecParser.io.data.ready := downRecFifo(1).io.enq.ready } //写入sram - sram.io.enw := + + val addrw = Reg(UInt(15.W)) + + when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ + addrw := downRecParser.io.subMsgReq.bits.address + } .otherwise{ + addrw := 0.U //清零方便调试识别 + } + } .elsewhen( io.sram_w.enw ){ + addrw := addrw + 1.U + } + + + io.sram_w.enr := false.B + + io.sram_w.enw := ( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) | (~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U)) - sram.io.addrw := - sram.io.dataw := downRecParser.io.data.bits + + io.sram_w.addr := addrw + io.sram_w.dataw := downRecParser.io.data.bits @@ -238,77 +260,86 @@ abstract class SlaveParserBase extends Module{ //上行接收 when( upRecParser.io.subMsgReq.fire ){ - when( isUpRecFifoPing ){ - isUpSubMsgValid(0) := true.B - + when( isUpRecPing ){ upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + upSubMsgInfo(0).workCnt := + Mux( + upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包 + (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写 + ), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt + ) upSubMsgInfo(0).source := 0.U - - //override 自身包 - when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ - when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram - } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U - } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U - } - } } .otherwise{ - isUpSubMsgValid(1) := true.B - upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + upSubMsgInfo(1).workCnt := + Mux( + upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包 + (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写 + ), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt + ) upSubMsgInfo(1).source := 1.U - //override 自身包 - when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ - when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram - } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U - } .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U - } - } } } - when( isUpRecFifoPing ){ + when( isUpRecPing ){ upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U), - sram.io.datar, upRecParser.io.data.bits) - - + io.sram_r.datar, upRecParser.io.data.bits) upRecParser.io.data.ready := upRecFifo(0).io.enq.ready + + upRecFifo(1).io.enq.valid := false.B + upRecFifo(1).io.enq.bits := 0.U } .otherwise{ + upRecFifo(0).io.enq.valid := false.B + upRecFifo(0).io.enq.bits := 0.U + upRecFifo(1).io.enq.valid := upRecParser.io.data.valid - upRecFifo(1).io.enq.bits := Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U), - sram.io.datar, upRecParser.io.data.bits) + upRecFifo(1).io.enq.bits := + Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U), + io.sram_r.datar, upRecParser.io.data.bits) upRecParser.io.data.ready := upRecFifo(1).io.enq.ready + } //读出SRAM - sram.io.enr := - ( isUpRecFifoPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) | - (~isUpRecFifoPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U)) + val addrr = Reg(UInt(15.W)) - sram.io.addrr := + when( upRecParser.io.subMsgReq.fire ){ + when(upRecParser.io.subMsgReq.bits.devIndex === localDevIndex){ + addrr := upRecParser.io.subMsgReq.bits.address + } .otherwise{ + addrr := 0.U //用于方便调试 + } + } .elsewhen( io.sram_r.enr ){ + addrr := addrr + 1.U + } + + io.sram_r.enw := false.B + io.sram_r.dataw := 0.U + io.sram_r.enr := + upRecParser.io.stateNext === STATE_PAYLOAD_DATA + // ( isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) | + // (~isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U)) + + io.sram_r.addr := addrr //子报文下行发送 - val isDownSendPing: Bool - val isUpSendPing: Bool - val isLastDevice: Bool + val isDownSendPing = RegInit(false.B) + val isUpSendPing = RegInit(false.B) + + val isLastDevice: Bool = false.B downSendGen.io.subMsgReq.valid := ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1)) @@ -318,16 +349,30 @@ abstract class SlaveParserBase extends Module{ when( downSendGen.io.subMsgReq.fire ){ //ready isDownSendPing := ~isDownSendPing when( isDownSendPing ){ + assert( isDownSubMsgValid(0) ) isDownSubMsgValid(0) := false.B } .otherwise{ + assert( isDownSubMsgValid(1) ) isDownSubMsgValid(1) := false.B } + } .elsewhen( downRecParser.io.subMsgReq.fire ){ + when( isDownRecPing ){ + isDownRecPing := ~isDownRecPing + assert( ~isDownSubMsgValid(0) ) + isDownSubMsgValid(0) := true.B + } .otherwise{ + assert( ~isDownSubMsgValid(1) ) + isDownSubMsgValid(1) := true.B + } } downRecFifo(0).io.deq <> downSendGen.io.data(0) downRecFifo(1).io.deq <> downSendGen.io.data(1) + downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1)) + + //子报文上行发送 upSendGen.io.subMsgReq.valid := @@ -338,22 +383,63 @@ abstract class SlaveParserBase extends Module{ when( upSendGen.io.subMsgReq.fire ){ //ready isUpSendPing := ~isUpSendPing when( isUpSendPing ){ + assert( isUpSubMsgValid(0) ) isUpSubMsgValid(0) := false.B } .otherwise{ + assert( isUpSubMsgValid(1) ) isUpSubMsgValid(1) := false.B } + }.elsewhen( upRecParser.io.subMsgReq.fire ){ + isUpRecPing := ~isUpRecPing + when( isUpRecPing ){ + assert( ~isUpSubMsgValid(0) ) + isUpSubMsgValid(0) := true.B + } .otherwise{ + assert( ~isUpSubMsgValid(1) ) + isUpSubMsgValid(1) := true.B + } } - upRecFifo(0).io.deq <> upSendGen.io.data(0) upRecFifo(1).io.deq <> upSendGen.io.data(1) + upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1)) - when(isLastDevice & downRecParser.io.stateCurr > ){ + + + + + + + + + + + + val isReadyToProbe = RegInit(false.B) + + + io.upOut <> upSendGen.io.send + io.downIn <> downRecParser.io.rec + + when( isLastDevice & isReadyToProbe ){ downSendGen.io.send <> upRecParser.io.rec + + io.downOut.valid := false.B + io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + io.upIn.ready := false.B + + } .otherwise{ + + io.downOut <> downSendGen.io.send + io.upIn <> upRecParser.io.rec + } +class SlaveParser extends SlaveParserBase + + diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index 555cbf6..7f1b838 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ -class SlaveRecParserIO extends Module{ +class SlaveRecParserIO extends Bundle{ val rec = Flipped( Decoupled(new AXIS_Bundle(8)) ) val data = Decoupled(UInt(8.W)) @@ -26,6 +26,24 @@ class SlaveRecParser extends Module{ val crc = Module(new crc32_8) + val STATE_IDLE = 0.U //空闲 + val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型 + val STATE_PAYLOAD_ADDR = 3.U //子报文地址 + val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度 + val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数 + val STATE_PAYLOAD_DATA = 6.U //子报文数据 + val STATE_CRC = 7.U //CRC校验 + val STATE_ERROR = 8.U // + val STATE_WAIT = 9.U + + + val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext + val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr + + io.isError := stateCurr === STATE_ERROR + io.rec.ready := true.B + crc.io.isEnable := stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD_INDEX_STYLE | @@ -49,20 +67,10 @@ class SlaveRecParser extends Module{ val FRAME_STYLE_PROBE = 1.U - val STATE_IDLE = 0.U //空闲 - val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 - val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型 - val STATE_PAYLOAD_ADDR = 3.U //子报文地址 - val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度 - val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数 - val STATE_PAYLOAD_DATA = 6.U //子报文数据 - val STATE_CRC = 7.U //CRC校验 - val STATE_ERROR = 8.U // - val STATE_WAIT = 9.U - val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext - val stateCurr = RegNext(stateNext, STATE_IDLE(4.W)); io.stateCurr := stateCurr + + val lengthCnt = Reg(UInt(11.W)) //动态计数器 val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 @@ -74,17 +82,12 @@ class SlaveRecParser extends Module{ - val frameLenAim = Reg(UInt(12.W)); io.frameReq.bits.frameLenAim := frameLenAim //帧长度目标 - val frameStyle = Reg(UInt(2.W)); io.frameReq.bits.frameStyle := frameStyle //包类型 - io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE) - val devIndex = Reg(UInt(14.W)); io.subMsgReq.bits.devIndex := devIndex // 子报文中设备索引 - val style = Reg(UInt(2.W)); io.subMsgReq.bits.style := style // 子报文类型 - val address = Reg(UInt(16.W)); io.subMsgReq.bits.address := address //子报文地址 - val operator = Reg(UInt(4.W)); io.subMsgReq.bits.operator := operator //子报文命令类型 - val length = Reg(UInt(12.W)); io.subMsgReq.bits.length := length //子报文负载长度 - val workCnt = Reg(UInt(16.W)); io.subMsgReq.bits.workCnt := workCnt //子报文工作计数 + io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE) + val frameHeader = Reg(new FrameHeader); io.frameReq.bits := frameHeader + io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA) + val subMsgHeader = Reg(new SubMsgHeader); io.subMsgReq.bits := subMsgHeader when( stateCurr === STATE_IDLE ){ lengthCnt := 0.U @@ -107,73 +110,73 @@ class SlaveRecParser extends Module{ } io.data.valid := stateCurr === STATE_PAYLOAD_DATA - io.data.bits := io.rec.bits + io.data.bits := io.rec.bits.tdata assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was recected by fifo!" ) when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){ - frameLenAim := io.rec.bits.tdata << 4 + frameHeader.frameLenAim := io.rec.bits.tdata << 4 } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){ - frameLenAim := frameLenAim | io.rec.bits.tdata(7,4) - frameStyle := io.rec.bits.tdata(1,0) + frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4) + frameHeader.frameStyle := io.rec.bits.tdata(1,0) } when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){ - devIndex := io.rec.bits.tdata << 6 + subMsgHeader.devIndex := io.rec.bits.tdata << 6 } .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){ - devIndex := devIndex | io.rec.bits.tdata(7,2) - style := io.rec.bits.tdata(1,0) + subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2) + subMsgHeader.style := io.rec.bits.tdata(1,0) } when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){ - address := io.rec.bits.tdata << 8 + subMsgHeader.address := io.rec.bits.tdata << 8 } .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){ - address := address | io.rec.bits.tdata + subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata } when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){ - operator := io.rec.bits.tdata(7,4) - length := io.rec.bits.tdata(3,0) << 8 + subMsgHeader.operator := io.rec.bits.tdata(7,4) + subMsgHeader.length := io.rec.bits.tdata(3,0) << 8 } .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){ - length := length | io.rec.bits.tdata(7,0) + subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0) } when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){ - workCnt := io.rec.bits.tdata(7,0) << 8 + subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8 } .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){ - workCnt := workCnt | io.rec.bits.tdata(7,0) + subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0) } stateNext := Mux1H(Seq( //必须使用上升沿触发，以避免前一帧长度超过预期 - ( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.axis.valid, STATE_HEADER, STATE_IDLE ), + ( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ), ( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_HEADER, + Mux( lengthCnt === 0.U, STATE_HEADER, MuxCase( STATE_ERROR, Array( - ( io.rec.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE, - ( io.rec.bits(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC, + ( io.rec.bits.tdata(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE, + ( io.rec.bits.tdata(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC, )) ) ), ( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR ) + Mux( lengthCnt === 0.U, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR ) ), ( stateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH ) + Mux( lengthCnt === 0.U, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH ) ), ( stateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT ) + Mux( lengthCnt === 0.U, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT ) ), ( stateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR, Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA ) ), ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR, - Mux( lengthCnt === ( subMsgLen - 1.U), - Mux( frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE + Mux( lengthCnt === ( subMsgHeader.length - 1.U), + Mux( frameLenCnt === frameHeader.frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE ), STATE_PAYLOAD_DATA ) ), ( stateCurr === STATE_CRC ) -> diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index b5a2ccb..634000b 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -10,30 +10,48 @@ class SubMsgTxInfo extends SubMsgHeader{ class SlaveSendGenIO extends Bundle{ - val data = for( 0 until 2 ) yield { Flipped( Decoupled(UInt(8.W)) ) } + val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) ) val frameReq = Flipped(Decoupled( new FrameHeader )) - val subMsgReq = Flipped(Decoupled( new SubMsgHeader )) + val subMsgReq = Flipped(Decoupled( new SubMsgTxInfo )) val send = Decoupled(new AXIS_Bundle(8)) val isError = Output(Bool()) } + + + class SlaveSendGen extends Module{ val io: SlaveSendGenIO = IO(new SlaveSendGenIO) val crc = Module(new crc32_8) + + val STATE_IDLE = 0.U //空闲 + val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_SUBMSG_HEADER = 2.U + val STATE_SUBMSG_DATA = 3.U + val STATE_CRC = 4.U //CRC校验 + val STATE_ERROR = 5.U + // val STATE_WAIT = 6.U + + + val stateNext = Wire(UInt(3.W)) + val stateCurr = RegNext(stateNext, STATE_IDLE) + + io.isError := stateCurr === STATE_ERROR + crc.io.isEnable := stateCurr === STATE_FRAME_HEADER | stateCurr === STATE_SUBMSG_HEADER | stateCurr === STATE_SUBMSG_DATA - crc.io.dataIn := tdata_submsg_data + crc.reset := reset.asBool | stateCurr === STATE_IDLE @@ -41,7 +59,7 @@ class SlaveSendGen extends Module{ val frameInfo = Reg(new FrameHeader) - val subMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) } + val subMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } val isPingFill = RegInit(false.B) val isPingEmit = RegInit(false.B) @@ -59,6 +77,9 @@ class SlaveSendGen extends Module{ } } + io.frameReq.ready := true.B + io.subMsgReq.ready := true.B + val lengthCnt = Reg(UInt(12.W)) val frameLenCnt = Reg(UInt(12.W)) @@ -82,25 +103,15 @@ class SlaveSendGen extends Module{ - val STATE_IDLE = 0.U //空闲 - val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 - val STATE_SUBMSG_HEADER = 2.U - val STATE_SUBMSG_DATA = 3.U - val STATE_CRC = 4.U //CRC校验 - val STATE_ERROR = 5.U - // val STATE_WAIT = 6.U - val stateNext = Wire(UInt(3.W)) - val stateCurr = RegNext(stateNext, STATE_IDLE(3.W)) - stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER), (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (64-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), (stateCurr === STATE_SUBMSG_DATA) -> Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 - Mux( frameLenCnt === frameInfo.lengthCnt, STATE_CRC, //主报文长度达到， 进CRC + Mux( frameLenCnt === frameInfo.frameLenAim, STATE_CRC, //主报文长度达到， 进CRC Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文 STATE_SUBMSG_DATA ), @@ -122,8 +133,8 @@ class SlaveSendGen extends Module{ val tdata_frame_header = Mux1H(Seq( - (lengthCnt === 0.U) -> frameLenAim(11,4), - (lengthCnt === 1.U) -> Cat( frameLenAim(3,0), 0.U(2.W), frameStyle), + (lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4), + (lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle), )) val tdata_submsg_header = Mux1H(Seq( @@ -142,7 +153,7 @@ class SlaveSendGen extends Module{ (subMsgInfoSel.source === 1.U) -> io.data(1).bits, )) - + crc.io.dataIn := tdata_submsg_data val tdata_crc = Mux1H(Seq( diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 1fdf7b7..8a78480 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -96,3 +96,9 @@ object testModule extends App { } +object testShinModule extends App { + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq( + ChiselGeneratorAnnotation(() => { new SlaveParser }), + )) +} + diff --git a/tb/shinTest/SlaveParserTb.v b/tb/shinTest/SlaveParserTb.v new file mode 100644 index 0000000..1ec23fd --- /dev/null +++ b/tb/shinTest/SlaveParserTb.v @@ -0,0 +1,117 @@ +`timescale 1 ns / 1 ps + + +module slaveParserTb( + +); + + reg clock; + reg reset; + + + +wire io_downIn_ready; +reg io_downIn_valid; +reg [7:0] io_downIn_bits_tdata; +reg io_downIn_bits_tlast; +reg io_downIn_bits_tuser; +reg io_downOut_ready; +wire io_downOut_valid; +wire [7:0] io_downOut_bits_tdata; +wire io_downOut_bits_tlast; +wire io_downOut_bits_tuser; +wire io_upIn_ready; +reg io_upIn_valid; +reg [7:0] io_upIn_bits_tdata; +reg io_upIn_bits_tlast; +reg io_upIn_bits_tuser; +reg io_upOut_ready; +wire io_upOut_valid; +wire [7:0] io_upOut_bits_tdata; +wire io_upOut_bits_tlast; +wire io_upOut_bits_tuser; +wire [14:0] io_sram_r_addr; +wire [7:0] io_sram_r_dataw; +reg [7:0] io_sram_r_datar; +wire io_sram_r_enw; +wire io_sram_r_enr; +wire [14:0] io_sram_w_addr; +wire [7:0] io_sram_w_dataw; +reg [7:0] io_sram_w_datar; +wire io_sram_w_enw; +wire io_sram_w_enr; + + + + + +s_SlaveParser SlaveParser( + .clock(clock), + .reset(reset), + .io_downIn_ready(io_downIn_ready), + .io_downIn_valid(io_downIn_valid), + .io_downIn_bits_tdata(io_downIn_bits_tdata), + .io_downIn_bits_tlast(io_downIn_bits_tlast), + .io_downIn_bits_tuser(io_downIn_bits_tuser), + .io_downOut_ready(io_downOut_ready), + .io_downOut_valid(io_downOut_valid), + .io_downOut_bits_tdata(io_downOut_bits_tdata), + .io_downOut_bits_tlast(io_downOut_bits_tlast), + .io_downOut_bits_tuser(io_downOut_bits_tuser), + .io_upIn_ready(io_upIn_ready), + .io_upIn_valid(io_upIn_valid), + .io_upIn_bits_tdata(io_upIn_bits_tdata), + .io_upIn_bits_tlast(io_upIn_bits_tlast), + .io_upIn_bits_tuser(io_upIn_bits_tuser), + .io_upOut_ready(io_upOut_ready), + .io_upOut_valid(io_upOut_valid), + .io_upOut_bits_tdata(io_upOut_bits_tdata), + .io_upOut_bits_tlast(io_upOut_bits_tlast), + .io_upOut_bits_tuser(io_upOut_bits_tuser), + .io_sram_r_addr(io_sram_r_addr), + .io_sram_r_dataw(io_sram_r_dataw), + .io_sram_r_datar(io_sram_r_datar), + .io_sram_r_enw(io_sram_r_enw), + .io_sram_r_enr(io_sram_r_enr), + .io_sram_w_addr(io_sram_w_addr), + .io_sram_w_dataw(io_sram_w_dataw), + .io_sram_w_datar(io_sram_w_datar), + .io_sram_w_enw(io_sram_w_enw), + .io_sram_w_enr(io_sram_w_enr) +); + + + + + + + + + +initial begin + clock = 0; + reset = 0; + + #100 + reset <= 1; + + #100 + reset <= 0; + + #160000 + $display("Time Out !!!"); + $stop; +end + +initial begin + forever begin #10 clock <= ~clock; end +end + +initial +begin + $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 + $dumpvars(0, slaveParserTb);//tb模块名称 +end + +endmodule +