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基本功能单元编译通过，开始搭建测试环境校对流水线

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This commit is contained in:
Ruige Lee
2025-04-11 17:57:47 +08:00
parent dabfc86983
commit 00a7b0fe6e
10 changed files with 493 additions and 259 deletions
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93
src/main/scala/backBoard/shin/SlaveRecParser.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
class SlaveRecParserIO extends Module{
class SlaveRecParserIO extends Bundle{
val rec = Flipped( Decoupled(new AXIS_Bundle(8)) )
val data = Decoupled(UInt(8.W))
@@ -26,6 +26,24 @@ class SlaveRecParser extends Module{
val crc = Module(new crc32_8)
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
io.isError := stateCurr === STATE_ERROR
io.rec.ready := true.B
crc.io.isEnable :=
stateCurr === STATE_HEADER |
stateCurr === STATE_PAYLOAD_INDEX_STYLE |
@@ -49,20 +67,10 @@ class SlaveRecParser extends Module{
val FRAME_STYLE_PROBE = 1.U
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
val stateCurr = RegNext(stateNext, STATE_IDLE(4.W)); io.stateCurr := stateCurr
val lengthCnt = Reg(UInt(11.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
@@ -74,17 +82,12 @@ class SlaveRecParser extends Module{
val frameLenAim = Reg(UInt(12.W)); io.frameReq.bits.frameLenAim := frameLenAim //帧长度目标
val frameStyle = Reg(UInt(2.W)); io.frameReq.bits.frameStyle := frameStyle //包类型
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE)
val devIndex = Reg(UInt(14.W)); io.subMsgReq.bits.devIndex := devIndex // 子报文中设备索引
val style = Reg(UInt(2.W)); io.subMsgReq.bits.style := style // 子报文类型
val address = Reg(UInt(16.W)); io.subMsgReq.bits.address := address //子报文地址
val operator = Reg(UInt(4.W)); io.subMsgReq.bits.operator := operator //子报文命令类型
val length = Reg(UInt(12.W)); io.subMsgReq.bits.length := length //子报文负载长度
val workCnt = Reg(UInt(16.W)); io.subMsgReq.bits.workCnt := workCnt //子报文工作计数
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE)
val frameHeader = Reg(new FrameHeader); io.frameReq.bits := frameHeader
io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)
val subMsgHeader = Reg(new SubMsgHeader); io.subMsgReq.bits := subMsgHeader
when( stateCurr === STATE_IDLE ){
lengthCnt := 0.U
@@ -107,73 +110,73 @@ class SlaveRecParser extends Module{
}
io.data.valid := stateCurr === STATE_PAYLOAD_DATA
io.data.bits := io.rec.bits
io.data.bits := io.rec.bits.tdata
assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was recected by fifo!" )
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
frameLenAim := io.rec.bits.tdata << 4
frameHeader.frameLenAim := io.rec.bits.tdata << 4
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameLenAim := frameLenAim | io.rec.bits.tdata(7,4)
frameStyle := io.rec.bits.tdata(1,0)
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
}
when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
devIndex := io.rec.bits.tdata << 6
subMsgHeader.devIndex := io.rec.bits.tdata << 6
} .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
devIndex := devIndex | io.rec.bits.tdata(7,2)
style := io.rec.bits.tdata(1,0)
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
subMsgHeader.style := io.rec.bits.tdata(1,0)
}
when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
address := io.rec.bits.tdata << 8
subMsgHeader.address := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
address := address | io.rec.bits.tdata
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
}
when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
operator := io.rec.bits.tdata(7,4)
length := io.rec.bits.tdata(3,0) << 8
subMsgHeader.operator := io.rec.bits.tdata(7,4)
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
length := length | io.rec.bits.tdata(7,0)
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
}
when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
workCnt := io.rec.bits.tdata(7,0) << 8
subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
workCnt := workCnt | io.rec.bits.tdata(7,0)
subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
}
stateNext :=
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.axis.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_HEADER,
Mux( lengthCnt === 0.U, STATE_HEADER,
MuxCase( STATE_ERROR, Array(
( io.rec.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
( io.rec.bits(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC,
( io.rec.bits.tdata(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
( io.rec.bits.tdata(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC,
))
)
),
( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
Mux( lengthCnt === 0.U, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
),
( stateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
Mux( lengthCnt === 0.U, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
),
( stateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
Mux( lengthCnt === 0.U, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
),
( stateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === ( subMsgLen - 1.U),
Mux( frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
Mux( lengthCnt === ( subMsgHeader.length - 1.U),
Mux( frameLenCnt === frameHeader.frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
), STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_CRC ) ->