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基本功能单元编译通过，开始搭建测试环境校对流水线

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This commit is contained in:
Ruige Lee
2025-04-11 17:57:47 +08:00
parent dabfc86983
commit 00a7b0fe6e
10 changed files with 493 additions and 259 deletions
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362
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -30,20 +30,33 @@ class ShareSRAMIO extends Bundle{
class SlaveParserIO extends Module{
class SlaveParserIO extends Bundle{
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val downOut = Decoupled(new AXIS_Bundle(8))
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val upOut = Decoupled(new AXIS_Bundle(8))
val sram_r = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
val sram_w = for( 0 until 2 ) yield { Flipped(new ShareSRAMIO) }
val sram_r = Flipped(new ShareSRAMIO)
val sram_w = Flipped(new ShareSRAMIO)
}
abstract class SlaveParserBase extends Module{
val io: SlaveParserIO = IO(new SlaveParserIO)
val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
@@ -54,96 +67,92 @@ abstract class SlaveParserBase extends Module{
val upSendGen = Module(new SlaveSendGen)
val devIndex = Reg(UInt(14.W)) //当前设备索引
val localDevIndex = Reg(UInt(14.W)) //当前设备索引
// 认为只有下行到下行，上行到上行模式，探针是独立发起操作
// val downSinkSel = Reg(Bool())
// val upSinkSel = Reg(Bool())
val downFrameInfo = Reg(new FrameHeader)
val downSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val downFrameInfo = Reg(new FrameHeader) //下行大包头
val upFrameInfo = Reg(new FrameHeader)
val upSubMsgInfo = for( 0 until 2 ) yield { Reg(new SubMsgHeader) }
val upFrameInfo = Reg(new FrameHeader) //上行大包头
val isDownSendBusy = downRecParser.io.frameReq.ready
val isUpSendBusy = upRecParser.io.frameReq.ready
val isDownSendBusy = downSendGen.io.frameReq.ready
val isUpSendBusy = upSendGen.io.frameReq.ready
val isDownSendPend = RegInit(false.B)
val isUpSendPend = RegInit(false.B)
// val isUpProbePending
//处理主报文
// when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
// // isUpSendPend := true.B //嗅探包不会立即发送，而是看门狗形式
// //downFrameInfo := downRecParser.io.frameReq.bits
// } .elsewhen( ){
//同时到来怎么办
when( downRecParser.io.frameReq.fire ){
when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
isUpSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
println("Warning! No busy protection!")
} .elsewhen( downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //下行来了一个普通包
isDownSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
println("Warning! No busy protection!")
}
} .elsewhen( upRecParser.io.frameReq.fire ){
when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
println("Probe Resp!")
} .elsewhen( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
isUpSendPend := true.B
upFrameInfo := upRecParser.io.frameReq.bits
println("Warning! No busy protection!")
}
}
val isDownSendProbe: Bool //下行探针
val isUpSendProbe: Bool //上行探针
val probeFrame: FrameHeader //固定化探针内容
downSendGen.io.frameReq.valid :=
isDownSendPend | isDownSendProbe //下行转发 | 下行探针
assert( OneHot(isDownSendPend, isDownSendProbe) )
downSendGen.io.frameReq.bits := Mux1H(Seq(
isDownSendPend -> downFrameInfo, //下行转发
isDownSendProbe -> probeFrame, //下行探针
))
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
} .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包
isDownSendPend := true.B
downFrameInfo := downRecParser.io.frameReq.bits
}
upSendGen.io.frameReq.valid :=
isUpSendPend | isUpSendProbe | //上行转发 | 上行探针 | 下行回环
assert( OneHot(isUpSendPend, isUpSendProbe) )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
isUpSendProbe -> probeFrame, //上行探针
, //下行回环
))
// when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
// println("Probe Resp!")
when( upSendGen.io.frameReq.fire ){
isUpSendPend := false.B
}
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
} .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
isUpSendPend := true.B
upFrameInfo := upRecParser.io.frameReq.bits
}
// val isDownSendProbe: Bool //下行探针
// val isUpSendProbe: Bool //上行探针
// val probeFrame: FrameHeader //固定化探针内容
downSendGen.io.frameReq.valid :=
isDownSendPend //| 下行转发
//isDownSendProbe //下行探针
// assert( OneHot(isDownSendPend, isDownSendProbe) )
downSendGen.io.frameReq.bits := Mux1H(Seq(
isDownSendPend -> downFrameInfo, //下行转发
//isDownSendProbe -> probeFrame, //下行探针
))
upSendGen.io.frameReq.valid :=
isUpSendPend //| 上行转发
//isUpSendProbe | // 上行探针
// assert( OneHot(isUpSendPend, isUpSendProbe) )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
//isUpSendProbe -> probeFrame, //上行探针
))
////////////////////////////////////////
//子报文
val isDownSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
val isUpSubMsgValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
val isUpSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
@@ -151,61 +160,50 @@ abstract class SlaveParserBase extends Module{
//接收子报文
val downSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) }
val upSubMsgInfo = for( i <- 0 until 2 ) yield { Reg(new SubMsgHeader) }
val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
val upSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
val downRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val upRecFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } //子报文负载
val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val isDownRecPing: Bool
val isUpRecPing: Bool
val isDownRecPing = RegInit(false.B)
val isUpRecPing = RegInit(false.B)
//下行接收
when( downRecParser.io.subMsgReq.fire ){
when( isDownRecPing ){
isDownSubMsgValid(0) := true.B
downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex
downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style
downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address
downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt
downSubMsgInfo(0).workCnt :=
Mux(
downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包
(downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作
), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt
)
downSubMsgInfo(0).source := 0.U
//override 自身包
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
} .otherwise{
isDownSubMsgValid(1) := true.B
downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style
downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address
downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt
downSubMsgInfo(1).workCnt :=
Mux(
downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包
(downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作
), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt
)
downSubMsgInfo(1).source := 1.U
//override 自身包
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
when( downRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
} .elsewhen( downRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
}
}
@@ -216,20 +214,44 @@ abstract class SlaveParserBase extends Module{
downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
downRecFifo(0).io.enq.bits := downRecParser.io.data.bits
downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
downRecFifo(1).io.enq.valid := false.B
downRecFifo(1).io.enq.bits := 0.U
} .otherwise{
downRecFifo(0).io.enq.valid := false.B
downRecFifo(0).io.enq.bits := 0.U
downRecFifo(1).io.enq.valid := downRecParser.io.data.valid
downRecFifo(1).io.enq.bits := downRecParser.io.data.bits
downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
}
//写入sram
sram.io.enw :=
val addrw = Reg(UInt(15.W))
when( downRecParser.io.subMsgReq.fire ){
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
addrw := downRecParser.io.subMsgReq.bits.address
} .otherwise{
addrw := 0.U //清零方便调试识别
}
} .elsewhen( io.sram_w.enw ){
addrw := addrw + 1.U
}
io.sram_w.enr := false.B
io.sram_w.enw :=
( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
(~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
sram.io.addrw :=
sram.io.dataw := downRecParser.io.data.bits
io.sram_w.addr := addrw
io.sram_w.dataw := downRecParser.io.data.bits
@@ -238,77 +260,86 @@ abstract class SlaveParserBase extends Module{
//上行接收
when( upRecParser.io.subMsgReq.fire ){
when( isUpRecFifoPing ){
isUpSubMsgValid(0) := true.B
when( isUpRecPing ){
upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style
upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address
upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt
upSubMsgInfo(0).workCnt :=
Mux(
upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包
(upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写
), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt
)
upSubMsgInfo(0).source := 0.U
//override 自身包
when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
} .otherwise{
isUpSubMsgValid(1) := true.B
upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style
upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address
upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt
upSubMsgInfo(1).workCnt :=
Mux(
upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包
(upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写
), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt
)
upSubMsgInfo(1).source := 1.U
//override 自身包
when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
when( upRecParser.io.subMsgReq.bits.operator === 1.U ) {//写 sparser -》sram
} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 2.U ) {//读 ram ->fifo
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
} .elsewhen( upRecParser.io.subMsgReq.bits.operator === 3.U ) {//读写 parser -》sram sram ->fifo
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
}
}
when( isUpRecFifoPing ){
when( isUpRecPing ){
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
upRecFifo(0).io.enq.bits :=
Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
sram.io.datar, upRecParser.io.data.bits)
io.sram_r.datar, upRecParser.io.data.bits)
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
upRecFifo(1).io.enq.valid := false.B
upRecFifo(1).io.enq.bits := 0.U
} .otherwise{
upRecFifo(0).io.enq.valid := false.B
upRecFifo(0).io.enq.bits := 0.U
upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
upRecFifo(1).io.enq.bits := Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
sram.io.datar, upRecParser.io.data.bits)
upRecFifo(1).io.enq.bits :=
Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U),
io.sram_r.datar, upRecParser.io.data.bits)
upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
}
//读出SRAM
sram.io.enr :=
( isUpRecFifoPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) |
(~isUpRecFifoPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U))
val addrr = Reg(UInt(15.W))
sram.io.addrr :=
when( upRecParser.io.subMsgReq.fire ){
when(upRecParser.io.subMsgReq.bits.devIndex === localDevIndex){
addrr := upRecParser.io.subMsgReq.bits.address
} .otherwise{
addrr := 0.U //用于方便调试
}
} .elsewhen( io.sram_r.enr ){
addrr := addrr + 1.U
}
io.sram_r.enw := false.B
io.sram_r.dataw := 0.U
io.sram_r.enr :=
upRecParser.io.stateNext === STATE_PAYLOAD_DATA
// ( isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) |
// (~isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U))
io.sram_r.addr := addrr
//子报文下行发送
val isDownSendPing: Bool
val isUpSendPing: Bool
val isLastDevice: Bool
val isDownSendPing = RegInit(false.B)
val isUpSendPing = RegInit(false.B)
val isLastDevice: Bool = false.B
downSendGen.io.subMsgReq.valid :=
( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))
@@ -318,16 +349,30 @@ abstract class SlaveParserBase extends Module{
when( downSendGen.io.subMsgReq.fire ){ //ready
isDownSendPing := ~isDownSendPing
when( isDownSendPing ){
assert( isDownSubMsgValid(0) )
isDownSubMsgValid(0) := false.B
} .otherwise{
assert( isDownSubMsgValid(1) )
isDownSubMsgValid(1) := false.B
}
} .elsewhen( downRecParser.io.subMsgReq.fire ){
when( isDownRecPing ){
isDownRecPing := ~isDownRecPing
assert( ~isDownSubMsgValid(0) )
isDownSubMsgValid(0) := true.B
} .otherwise{
assert( ~isDownSubMsgValid(1) )
isDownSubMsgValid(1) := true.B
}
}
downRecFifo(0).io.deq <> downSendGen.io.data(0)
downRecFifo(1).io.deq <> downSendGen.io.data(1)
downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))
//子报文上行发送
upSendGen.io.subMsgReq.valid :=
@@ -338,22 +383,63 @@ abstract class SlaveParserBase extends Module{
when( upSendGen.io.subMsgReq.fire ){ //ready
isUpSendPing := ~isUpSendPing
when( isUpSendPing ){
assert( isUpSubMsgValid(0) )
isUpSubMsgValid(0) := false.B
} .otherwise{
assert( isUpSubMsgValid(1) )
isUpSubMsgValid(1) := false.B
}
}.elsewhen( upRecParser.io.subMsgReq.fire ){
isUpRecPing := ~isUpRecPing
when( isUpRecPing ){
assert( ~isUpSubMsgValid(0) )
isUpSubMsgValid(0) := true.B
} .otherwise{
assert( ~isUpSubMsgValid(1) )
isUpSubMsgValid(1) := true.B
}
}
upRecFifo(0).io.deq <> upSendGen.io.data(0)
upRecFifo(1).io.deq <> upSendGen.io.data(1)
upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))
when(isLastDevice & downRecParser.io.stateCurr > ){
val isReadyToProbe = RegInit(false.B)
io.upOut <> upSendGen.io.send
io.downIn <> downRecParser.io.rec
when( isLastDevice & isReadyToProbe ){
downSendGen.io.send <> upRecParser.io.rec
io.downOut.valid := false.B
io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
io.upIn.ready := false.B
} .otherwise{
io.downOut <> downSendGen.io.send
io.upIn <> upRecParser.io.rec
}
class SlaveParser extends SlaveParserBase