基本功能单元编译通过，开始搭建测试环境校对流水线

src/main/scala/backBoard/shin/ShinTop.scala

@@ -1,54 +1,54 @@
-package BACK
+// package BACK
 
-import chisel3._
-import chisel3.util._
+// import chisel3._
+// import chisel3.util._
 
 
-class ShinTopIO extends Bundle{
-	val clk8x = Input(Bool())
-	val modeSel = Input(Bool())\
+// class ShinTopIO extends Bundle{
+// 	val clk8x = Input(Bool())
+// 	val modeSel = Input(Bool())\
 	
-  val dDatIn   = Input(Bool())
-  val dDatOut  = Output(Bool())
-  val uDatIn   = Input(Bool())
-  val uDatOut  = Output(Bool())
+//   val dDatIn   = Input(Bool())
+//   val dDatOut  = Output(Bool())
+//   val uDatIn   = Input(Bool())
+//   val uDatOut  = Output(Bool())
 
-	val qspi = 
-	val interrupt = Output(Bool())
-	val ctrl      = Input(UInt(4.W))
-}
+// 	val qspi = 
+// 	val interrupt = Output(Bool())
+// 	val ctrl      = Input(UInt(4.W))
+// }
 
 
 
-class ShinTop extends Module{
-  val io: ShinTopIO = IO(new ShinTopIO)
+// class ShinTop extends Module{
+//   val io: ShinTopIO = IO(new ShinTopIO)
 
-  val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
-	val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
+//   val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
+// 	val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
 
-	val slaveParser  = Module(new SlaveParser )
-	val masterParser = Module(new MasterParser)
+// 	val slaveParser  = Module(new SlaveParser )
+// 	val masterParser = Module(new MasterParser)
 
-	val sram = Module(new ShareSRAMDP)
+// 	val sram = Module(new ShareSRAMDP)
 
-	val interface = Module(new Interface)
+// 	val interface = Module(new Interface)
 
 
-  sram.io.addrA   := Input(UInt(15.W))
-  sram.io.datawA  := Input( UInt(8.W) )
-  sram.io.datarA  := Output( UInt(8.W) )
-  sram.io.enwA    := Input(Bool())
-  sram.io.enrA    := Input(Bool())
-  sram.io.clockA  := Input(Bool())
+//   sram.io.addrA   := Input(UInt(15.W))
+//   sram.io.datawA  := Input( UInt(8.W) )
+//   sram.io.datarA  := Output( UInt(8.W) )
+//   sram.io.enwA    := Input(Bool())
+//   sram.io.enrA    := Input(Bool())
+//   sram.io.clockA  := Input(Bool())
 
-  sram.io.addrB  := Input(UInt(15.W))
-  sram.io.datawB := Input( UInt(8.W) )
-  sram.io.datarB := Output( UInt(8.W) )
-  sram.io.enwB   := Input(Bool())
-  sram.io.enrB   := Input(Bool())
-  sram.io.clockB := Input(Bool())
+//   sram.io.addrB  := Input(UInt(15.W))
+//   sram.io.datawB := Input( UInt(8.W) )
+//   sram.io.datarB := Output( UInt(8.W) )
+//   sram.io.enwB   := Input(Bool())
+//   sram.io.enrB   := Input(Bool())
+//   sram.io.clockB := Input(Bool())
 
 
 
 
-}
+// }