基本功能单元编译通过，开始搭建测试环境校对流水线

2025-04-11 17:57:47 +08:00
parent dabfc86983
commit 00a7b0fe6e
10 changed files with 493 additions and 259 deletions
--- a/src/main/scala/backBoard/shin/ShareSRAM.scala
+++ b/src/main/scala/backBoard/shin/ShareSRAM.scala
@@ -24,11 +24,11 @@ class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
      val clockB = Input(Bool())

  }
-  val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
+  val io: ShareSRAMDPIO = IO(new ShareSRAMDPIO)

- setInline("MirrorSRAMDP.v",
+ setInline("ShareSRAMDP.v",
              """
-      | module MirrorSRAMDP(
+      | module ShareSRAMDP(
      |  	input [7:0]  datawA,
      |  	input [14:0]   addrA,
      |  	input enwA,