2025-01-31 23:33:43 +08:00
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TARGET=riscv64-unknown-elf
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RVCC=$(TARGET)-gcc
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RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
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2025-02-10 14:38:49 +08:00
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ISR_MARCH=-march=rv32i -mabi=ilp32
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APP_MARCH=-march=rv32i -mabi=ilp32
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ISR_CFLAGS=-O2
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APP_CFLAGS=-O2
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2025-09-22 15:43:14 +08:00
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SPI_TYPE ?= -spi 0
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TRANS_CODE ?=
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DEVCLK ?= --dev1 0 90 --dev2 0 -90
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CDRCLK ?= --clk 0 40
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2025-09-22 17:52:12 +08:00
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CDR_TYPE ?= -cdr 0
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2025-09-22 15:43:14 +08:00
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2025-01-31 23:33:43 +08:00
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ifeq "$(RVCCVERSION)" "12.2.0"
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2025-02-10 14:38:49 +08:00
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ISR_MARCH=-march=rv32izicsr -mabi=ilp32
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APP_MARCH=-march=rv32izicsr -mabi=ilp32
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2025-01-31 23:33:43 +08:00
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endif
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2023-06-20 18:26:59 +08:00
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2024-09-10 18:39:35 +08:00
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.PHONY: compile tb wave
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2023-06-20 18:26:59 +08:00
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2025-04-11 17:57:47 +08:00
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shin:
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rm -f ./generated/shin/*
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2025-09-11 18:57:58 +08:00
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rm -f ./generated/SimCDR/*
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2025-04-11 17:57:47 +08:00
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sbt "test:runMain test.testShinModule"
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testShin:
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2025-09-22 17:52:12 +08:00
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python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
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2025-09-09 01:21:02 +08:00
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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-D IVERILOG_COMPILE \
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./tb/shinTest/ShinTopSpiTb.v
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2025-09-02 11:10:05 +08:00
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vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
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2025-09-08 16:47:30 +08:00
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python3 ./tb/shinTest/check_testcase.py
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2025-07-28 22:41:02 +08:00
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2025-09-06 16:10:49 +08:00
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testShinClk:
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2025-09-22 17:52:12 +08:00
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python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
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2025-09-06 16:10:49 +08:00
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./tb/build/shinTest_clk.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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2025-09-07 00:10:41 +08:00
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-D IVERILOG_COMPILE \
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2025-09-06 16:10:49 +08:00
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./tb/shinTest/ShinTopSpiTb_clk.v
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vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
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2025-09-08 16:47:30 +08:00
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python3 ./tb/shinTest/check_testcase.py
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2025-09-06 16:10:49 +08:00
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|
2025-08-28 20:03:42 +08:00
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testCDR:
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2025-09-22 15:43:14 +08:00
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python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
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2025-08-28 20:03:42 +08:00
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iverilog -Wall \
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-o ./tb/build/simCDR.iverilog \
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-y ./generated/SimCDR \
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-I ./generated/SimCDR \
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-D RANDOMIZE_REG_INIT \
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2025-09-07 00:10:41 +08:00
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-D IVERILOG_COMPILE \
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2025-08-28 20:03:42 +08:00
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./tb/shinTest/SimCDRTb.v
|
2025-09-06 17:50:17 +08:00
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vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst
|
2025-08-28 20:03:42 +08:00
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|
2025-08-19 09:10:43 +08:00
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testFilter:
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./tb/shinTest/test_filter.py
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vcdFilter:
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gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &
|
2025-04-14 16:43:10 +08:00
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|
2025-09-02 11:10:05 +08:00
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fstShin:
|
2025-09-06 17:50:17 +08:00
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gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
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fstShinClk:
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gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
|
2025-09-02 11:10:05 +08:00
|
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|
|
2023-11-14 17:03:19 +08:00
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|
ef:
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sbt "test:runMain test.testModule"
|
2023-07-17 09:26:20 +08:00
|
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fst:
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gtkwave ./tb/build/wave.fst &
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|
2025-02-27 12:55:34 +08:00
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|
debug_hlm:
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|
gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &
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|
2023-07-28 15:38:46 +08:00
|
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2025-04-14 16:43:10 +08:00
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2023-07-28 15:38:46 +08:00
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