2025-04-24 17:31:44 +08:00
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// package BACK
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2025-04-02 16:40:25 +08:00
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2025-04-24 17:31:44 +08:00
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// import chisel3._
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// import chisel3.util._
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2025-04-02 16:40:25 +08:00
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2025-04-24 17:31:44 +08:00
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// class MasterParserIO extends Module{
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// val downOut = Decoupled(new AXIS_Bundle(8))
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// val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
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2025-04-24 17:31:44 +08:00
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// val sram_r = Flipped(new ShareSRAMIO)
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// val sram_w = Flipped(new ShareSRAMIO)
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// val req = Valid(new Bundle{
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// val length = UInt(12.W)
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// })
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// val rsp = Valid(new Bundle{
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// val isError = Bool()
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// val length = UInt(12.W)
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// })
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2025-04-24 17:31:44 +08:00
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// }
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2025-04-02 16:40:25 +08:00
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2025-04-24 17:31:44 +08:00
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// abstract class MasterParserBase extends Module{
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// val io: MasterParserIO = IO(new MasterParserIO)
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// val sendCnt = Reg(UInt(11.W))
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// val sendLen = Reg(UInt(11.W))
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2025-04-24 17:31:44 +08:00
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// val reqReady = RegInit(true.B)
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// val sendAddr = Reg(UInt(12.W))
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// io.req.ready := reqReady
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// when( io.req.fire ){
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// reqReady := false.B
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// } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
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// reqReady := true.B
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// }
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2025-04-16 16:49:42 +08:00
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2025-04-24 17:31:44 +08:00
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// when( io.req.fire ){
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// sendLen := io.req.bits.length
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// sendCnt := 0.U
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// } .elsewhen( io.downOut.fire ){
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// sendCnt := sendCnt + 1.U
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// }
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2025-04-16 16:49:42 +08:00
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2025-04-24 17:31:44 +08:00
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// when( reqReady ){
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// sendAddr := 0.U
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// } .elsewhen( io.downOut.fire ){
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// sendAddr := sendAddr + 1.U
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// }
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// io.sram_r.enr :=
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// io.req.fire | io.downOut.fire
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// io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
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// io.downOut.valid := ~reqReady
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// io.downOut.bits.tdata := io.req.bits.datar
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// io.downOut.bits.tuser := false.B
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// io.downOut.bits.tlast := sendCnt === sendLen
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2025-04-24 17:31:44 +08:00
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// val recAddr = Reg(UInt(12.W))
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// io.upIn.ready := true.B
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// io.sram_w.enw := io.upIn.fire
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// io.sram_w.addr := recAddr
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// io.sram_w.dataw := io.upIn.bits.tdata
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2025-04-24 17:31:44 +08:00
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// when( io.upIn.fire ){
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// when( io.upIn.bits.tlast ){
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// recAddr := 0.U
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// } .otherwise{
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// recAddr := recAddr + 1.U
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// }
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// }
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// io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
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// io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
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// io.rsp.bits.length := recAddr
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2025-04-16 16:49:42 +08:00
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2025-04-24 17:31:44 +08:00
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// }
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2025-04-16 16:49:42 +08:00
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2025-04-24 17:31:44 +08:00
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// class MasterParser extends MasterParserBase{
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2025-04-16 16:49:42 +08:00
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2025-04-24 17:31:44 +08:00
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// }
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