eb001/src/main/scala/backBoard/BackBoardSlv.scala

package BACK

import chisel3._
import chisel3.util._



class BackBoardSlvIO extends Bundle{

  val reset_calib = Input(Bool())
  val oser_pclk = Input(Bool())
  val oser_fclk = Input(Bool())
  val ides_pclk = Input(Bool())
  val ides_fclk = Input(Bool())

  val lvds_down_din  = Input(Bool())
  val lvds_down_dout = Output(Bool())
  val lvds_up_din    = Input(Bool())
  val lvds_up_dout   = Output(Bool())
}


abstract class BackBoardSlvBase extends Module{
  val io: BackBoardSlvIO = IO(new BackBoardSlvIO)

  val lvdsSlv = Module(new Lvds_Bus_Slave)

  lvdsSlv.io.rst_n       := ~reset.asBool()
  lvdsSlv.io.reset_calib := io.reset_calib   
  lvdsSlv.io.oser_pclk   := io.oser_pclk
  lvdsSlv.io.oser_fclk   := io.oser_fclk
  lvdsSlv.io.ides_pclk   := io.ides_pclk
  lvdsSlv.io.ides_fclk   := io.ides_fclk
  

  lvdsSlv.io.lvds_down_din  := io.lvds_down_din 
  io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
  lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
  io.lvds_up_dout   := lvdsSlv.io.lvds_up_dout

  val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
  val downReg     = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
  val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
}


trait BackBoardSlvDown{ this: BackBoardSlvBase =>


  val downCnt = Reg(UInt(6.W))


  when( lvdsSlv.io.downstream_rx_data_valid ){
    downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
    downCnt := downCnt + 1.U
  } .otherwise{
    downCnt := 0.U
  }

  when( lvdsSlv.io.downstream_rx_crc_valid ){
    when( ~lvdsSlv.io.downstream_rx_crc_err ){
      downReg := downRegTemp
    }
  }

}

trait BackBoardSlvUp{ this: BackBoardSlvBase =>

  val upCnt = Reg(UInt(6.W))

  lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)

  when( lvdsSlv.io.upstream_tx_data_ready ){
    when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){
      upCnt := 0.U
    } .otherwise{
      upCnt := upCnt + 1.U
    }
  }


}