58 lines
1.2 KiB
Scala
58 lines
1.2 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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class BackBoardMstIO extends Bundle{
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val downStreamReqDat = Input( Bool() )
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val downStreamRespdat = Output(Bool())
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val CS = Input(Bool())
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val MISO = Output(Bool())
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val MOSI = Input(Bool())
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val SCK = Input(Bool())
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val interrupt = Output(Bool())
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val clk4 = Input( Bool() )
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val reset = Input(Bool())
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}
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class BackBoardMst extends RawModule{
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val io: BackBoardMstIO = IO(new BackBoardMstIO)
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withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
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val spi = Module( new SpiSlv )
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val in = Module( new CDR4MultiIn )
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val out = Module( new CDROutBus )
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spi.io.CS := io.CS
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io.MISO := spi.io.MISO
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spi.io.MOSI := io.MOSI
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io.interrupt := spi.io.interrupt
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spi.io.CDRIn <> in.io.latDat
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spi.io.CDROut <> out.io.pkgDat
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in.io.clk4 := io.clk4
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in.io.dat := io.downStreamReqDat
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io.downStreamRespdat := out.io.dat
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spi.clock := io.SCK.asClock
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in.clock := io.SCK.asClock
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out.clock := io.SCK.asClock
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spi.reset := io.reset.asAsyncReset
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in.reset := io.reset.asAsyncReset
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out.reset := io.reset.asAsyncReset
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}
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}
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