package BACK

import chisel3._
import chisel3.util._


class BackBoardMstIO extends Bundle{
  val downStreamReqDat  = Input( Bool() )
  val downStreamRespdat = Output(Bool())

  val CS   = Input(Bool())
  val MISO = Output(Bool())
  val MOSI = Input(Bool())
  val SCK  = Input(Bool())

  val interrupt = Output(Bool())

  val clk4            = Input( Bool() )

  val reset = Input(Bool())
}


class BackBoardMst extends RawModule{
  val io: BackBoardMstIO = IO(new BackBoardMstIO)

  withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
    val spi = Module( new SpiSlv )
    val in  = Module( new CDR4MultiIn )
    val out = Module( new CDROutBus )

    spi.io.CS   := io.CS
    io.MISO     := spi.io.MISO
    spi.io.MOSI := io.MOSI

    io.interrupt := spi.io.interrupt

    spi.io.CDRIn  <> in.io.latDat
    spi.io.CDROut <> out.io.pkgDat

    in.io.clk4 := io.clk4

    in.io.dat  := io.downStreamReqDat
    io.downStreamRespdat := out.io.dat

    spi.clock := io.SCK.asClock
    in.clock  := io.SCK.asClock
    out.clock := io.SCK.asClock

    spi.reset := io.reset.asAsyncReset
    in.reset  := io.reset.asAsyncReset
    out.reset := io.reset.asAsyncReset
  }
}