2024-10-25 17:46:21 +08:00
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2024-10-28 15:51:12 +08:00
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2024-10-28 18:01:25 +08:00
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.extern main
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2025-01-16 16:34:48 +08:00
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.extern plic_handle
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.globl prog_start
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2024-10-28 18:01:25 +08:00
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.section .text.init
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2024-10-28 15:51:12 +08:00
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2024-10-28 18:01:25 +08:00
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_prog_start:
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2024-10-29 17:32:17 +08:00
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2025-01-15 15:44:29 +08:00
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la t0, trap_entry
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csrw mtvec, t0
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2025-01-16 16:34:48 +08:00
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li t0, 1 << 11
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csrw mie, t0
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csrr t0, mstatus
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ori t0, t0, 1<<3
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csrw mstatus, t0
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2025-01-15 15:44:29 +08:00
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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li sp, 0x40011000
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2024-10-28 18:01:25 +08:00
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call main
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2024-10-28 15:51:12 +08:00
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2024-10-28 18:01:25 +08:00
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ecall
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2024-10-28 15:51:12 +08:00
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2024-10-25 17:46:21 +08:00
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2024-10-28 18:01:25 +08:00
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2025-01-16 16:34:48 +08:00
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.balign 32
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.section .trap_entry, "ax", %progbits
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trap_entry:
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addi sp,sp,-136
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sw ra,4(sp)
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sw sp,8(sp)
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sw gp,12(sp)
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sw tp,16(sp)
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sw t0,20(sp)
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sw t1,24(sp)
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sw t2,28(sp)
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sw s0,32(sp)
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sw s1,36(sp)
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sw a0,40(sp)
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sw a1,44(sp)
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sw a2,48(sp)
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sw a3,52(sp)
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sw a4,56(sp)
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sw a5,60(sp)
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sw a6,64(sp)
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sw a7,68(sp)
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sw s2,72(sp)
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sw s3,76(sp)
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sw s4,80(sp)
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sw s5,84(sp)
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sw s6,88(sp)
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sw s7,92(sp)
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sw s8,96(sp)
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sw s9,100(sp)
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sw s10,104(sp)
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sw s11,108(sp)
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sw t3,112(sp)
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sw t4,116(sp)
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sw t5,120(sp)
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sw t6,124(sp)
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csrr t0, mstatus # 读取 mstatus 寄存器
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andi t0, t0, ~(1 << 3) # 清除 MIE 位 (全局中断禁用)
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csrw mstatus, t0 # 写回 mstatus 寄存器
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call plic_handle
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csrr t0, mstatus
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ori t0, t0, 1<<3
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csrw mstatus, t0
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lw ra,4(sp)
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lw sp,8(sp)
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lw gp,12(sp)
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lw tp,16(sp)
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lw t0,20(sp)
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lw t1,24(sp)
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lw t2,28(sp)
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lw s0,32(sp)
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lw s1,36(sp)
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lw a0,40(sp)
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lw a1,44(sp)
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lw a2,48(sp)
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lw a3,52(sp)
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lw a4,56(sp)
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lw a5,60(sp)
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lw a6,64(sp)
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lw a7,68(sp)
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lw s2,72(sp)
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lw s3,76(sp)
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lw s4,80(sp)
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lw s5,84(sp)
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lw s6,88(sp)
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lw s7,92(sp)
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lw s8,96(sp)
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lw s9,100(sp)
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lw s10,104(sp)
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lw s11,108(sp)
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lw t3,112(sp)
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lw t4,116(sp)
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lw t5,120(sp)
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lw t6,124(sp)
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addi sp,sp,136
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mret
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2024-10-28 18:01:25 +08:00
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