59 lines
1.7 KiB
Scala
59 lines
1.7 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
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class SimpleGpioIO extends Bundle{
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val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
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val tld = new DecoupledIO(new TLBundleD(edge.bundle))
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val out = Output(UInt(32.W))
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val in = Input(UInt(32.W))
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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}
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val io: SimpleGpioIO = IO(new SimpleGpioIO)
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val isWriteGpio = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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val isReadGpio = io.tla.fire & io.tla.bits.address(3,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
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// val isWriteDir = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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val isReadIsLast = io.tla.fire & io.tla.bits.address(3,0) === "h8".U & ( io.tla.bits.opcode === 4.U )
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io.isOnline := false.B
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val tldValid = RegInit(false.B)
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val tlaInfo = Reg(new TLBundleA(edge.bundle))
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val isRead = Reg(Bool())
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io.out := RegEnable( io.tla.bits.data, 0.U(32.W), isWriteGpio )
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when( io.tld.fire ){
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tldValid := false.B
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} .elsewhen( io.tla.fire ){
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tldValid := true.B
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tlaInfo := io.tla.bits
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isRead := io.tla.bits.opcode === 4.U
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}
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io.tla.ready := true.B
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io.tld.valid := tldValid
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when(isRead) {
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io.tld.bits := edge.AccessAck(tlaInfo,
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Mux( tlaInfo.address(3,0) === "h0".U, io.in, Mux( tlaInfo.address(3,0) === "h8".U, io.isLast, 0.U ) )
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)
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} .otherwise {
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io.tld.bits := edge.AccessAck(tlaInfo)
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}
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}
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