package BACK

import chisel3._
import chisel3.util._

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._


class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
  class SimpleGpioIO extends Bundle{
    val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
    val tld = new DecoupledIO(new TLBundleD(edge.bundle))

    val out = Output(UInt(32.W))
    val in  = Input(UInt(32.W))


    val isOnline = Output(Bool())
    val isLast   = Input(Bool())

  }

  val io: SimpleGpioIO = IO(new SimpleGpioIO)

  val isWriteGpio  = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
  val isReadGpio   = io.tla.fire & io.tla.bits.address(3,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
  // val isWriteDir   = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
  val isReadIsLast = io.tla.fire & io.tla.bits.address(3,0) === "h8".U & ( io.tla.bits.opcode === 4.U )


  io.isOnline := false.B

  val tldValid = RegInit(false.B)
  val tlaInfo = Reg(new TLBundleA(edge.bundle))
  val isRead = Reg(Bool())

  io.out := RegEnable( io.tla.bits.data, 0.U(32.W), isWriteGpio )

  when( io.tld.fire ){
    tldValid := false.B
  } .elsewhen( io.tla.fire ){
    tldValid := true.B
    tlaInfo := io.tla.bits
    isRead := io.tla.bits.opcode === 4.U
  }

  io.tla.ready := true.B
  io.tld.valid := tldValid

  when(isRead) {
    io.tld.bits := edge.AccessAck(tlaInfo, 
      Mux( tlaInfo.address(3,0) === "h0".U, io.in, Mux( tlaInfo.address(3,0) === "h8".U, io.isLast, 0.U ) )
    )
  } .otherwise {
    io.tld.bits := edge.AccessAck(tlaInfo)
  }
}