!"#$! &XSET CREATE_BUILD 214" "
<0A>CREATE USER IF NOT EXISTS "SA" SALT '570c662a4aed13d7' HASH '684ffa8cfe9ed7d665d50297eddd3152fc77e49e35da93e6c9cefb0c5e3c2533' ADMIN#
<0A>CREATE CACHED TABLE "PUBLIC"."flyway_schema_history"(
"installed_rank" INTEGER NOT NULL,
"version" CHARACTER VARYING(50),
"description" CHARACTER VARYING(200) NOT NULL,
"type" CHARACTER VARYING(20) NOT NULL,
"script" CHARACTER VARYING(1000) NOT NULL,
"checksum" INTEGER,
"installed_by" CHARACTER VARYING(100) NOT NULL,
"installed_on" TIMESTAMP DEFAULT CURRENT_TIMESTAMP NOT NULL,
"execution_time" INTEGER NOT NULL,
"success" BOOLEAN NOT NULL
)$ !
aCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_6" ON "PUBLIC"."flyway_schema_history"("installed_rank")% %
<0A>ALTER TABLE "PUBLIC"."flyway_schema_history" ADD CONSTRAINT "PUBLIC"."flyway_schema_history_pk" PRIMARY KEY("installed_rank") INDEX "PUBLIC"."PRIMARY_KEY_6"& !
nCREATE INDEX "PUBLIC"."flyway_schema_history_s_idx" ON "PUBLIC"."flyway_schema_history"("success" NULLS FIRST)'
<0A>CREATE CACHED TABLE "PUBLIC"."DEPENDENCY_SOURCE"(
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= CounterPreset[7:0];
end
else
Counter[7:0] <= Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= 1'b0;
else
begin
if(CountEq0)
Mdc <= ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= CounterPreset[7:0];
end
else
Counter[7:0] <= Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= 1'b0;
else
begin
if(CountEq0)
Mdc <= ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg [7:0] Counter;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
// Counter counts half period
val Counter = RegInit( 1.U(8.W) )
val CountEq0 = Counter === 0.U
when( CountEq0 ) {
Counter := CounterPreset
} .otherwise{
Counter := Counter - 1.U
}
// Mdc is asserted every other half period
val Mdc = RegInit(false.B)
when(CountEq0) {
Mdc := ~Mdc
}
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= 1'b0;
else
begin
if(CountEq0)
Mdc <= ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg [7:0] Counter;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
// Counter counts half period
val Counter = RegInit( 1.U(8.W) )
val CountEq0 = Counter === 0.U
val MdcEn = CountEq0 & ~Mdc;
val MdcEn_n = CountEq0 & Mdc;
when( CountEq0 ) {
Counter := CounterPreset
} .otherwise{
Counter := Counter - 1.U
}
// Mdc is asserted every other half period
val Mdc = RegInit(false.B)
when(CountEq0) {
Mdc := ~Mdc
}
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
// Counter counts half period
val Counter = RegInit( 1.U(8.W) )
val Mdc = RegInit(false.B) // Output clock
val CountEq0 = Counter === 0.U
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
when( CountEq0 ) {
Counter := CounterPreset
} .otherwise{
Counter := Counter - 1.U
}
// Mdc is asserted every other half period
when(CountEq0) {
Mdc := ~Mdc
}
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
// Counter counts half period
val Counter = RegInit( 1.U(8.W) )
val Mdc = RegInit(false.B) // Output clock
val CountEq0 = Counter === 0.U
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
when( CountEq0 ) {
Counter := CounterPreset
} .otherwise{
Counter := Counter - 1.U
}
// Mdc is asserted every other half period
when(CountEq0) {
Mdc := ~Mdc
}
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
val mdi = Input( Bool()) // MII Management Data In
val mdc = Output(Bool()) // MII Management Data Clock
val mdo = Output(Bool()) // MII Management Data Output
val mdoEn = Output(Bool()) // MII Management Data Output Enable
}
class MIIMBase extends Module{
class MIIMIO extends Bundle{
}
}
/** Connecting the Clock Generator Module */
trait MIIMClockGen{ this: MACBase =>
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
// Counter counts half period
val Counter = RegInit( 1.U(8.W) )
val Mdc = RegInit(false.B) // Output clock
val CountEq0 = Counter === 0.U
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
when( CountEq0 ) {
Counter := CounterPreset
} .otherwise{
Counter := Counter - 1.U
}
// Mdc is asserted every other half period
when(CountEq0) {
Mdc := ~Mdc
}
}
trait MIIM { This: =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
}
ED7D77B71BE8FC3C4AC656872990DDAD-
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
import chisel3._
import chisel3.util
class MIIMIO extends Bundle{
val mdi = Input( Bool()) // MII Management Data In
val mdc = Output(Bool()) // MII Management Data Clock
val mdo = Output(Bool()) // MII Management Data Output
val mdoEn = Output(Bool()) // MII Management Data Output Enable
}
class MIIMBase extends Module{
class MIIMIO extends Bundle{
}
}
/** Connecting the Clock Generator Module */
trait MIIMClockGen{ this: MIIMBase =>
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
// Counter counts half period
val Counter = RegInit( 1.U(8.W) )
val Mdc = RegInit(false.B) // Output clock
val CountEq0 = Counter === 0.U
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
when( CountEq0 ) {
Counter := CounterPreset
} .otherwise{
Counter := Counter - 1.U
}
// Mdc is asserted every other half period
when(CountEq0) {
Mdc := ~Mdc
}
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end else begin
if(LatchByte[1])
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
}
} .otherwise{
when(LatchByte[1]){
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
}
} .otherwise{
when(LatchByte[1]){
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
}
} .otherwise{
when(LatchByte[1]){
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail <= ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .otherwise{
when(LatchByte[1]){
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .otherwise{
when(LatchByte[1]){
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .otherwise{
when(LatchByte.extract(1)){
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .elsewhen(LatchByte.extract(1)){
Prsd <= {ShiftReg(6:0), Mdi, Prsd(7,0)};
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .elsewhen(LatchByte.extract(1)){
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
}
}
}
}
assign ShiftedBit = ShiftReg[7];
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .elsewhen(LatchByte.extract(1)){
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
}
}
}
}
val ShiftedBit = ShiftReg.extract(7);
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .elsewhen(LatchByte.extract(1)){
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
}
}
}
}
val ShiftedBit = ShiftReg.extract(7)
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .elsewhen(LatchByte.extract(1)){
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
}
}
}
}
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
}
} .elsewhen(LatchByte.extract(1)){
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
}
}
}
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
}
trait MIIM { This: MIIMBase=>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
}
trait MIIM { this: MIIMBase =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
}
trait MIIM { this: MIIMBase =>
input Clk; // Host Clock
input Reset; // General Reset
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
val EndBusy = RegInit(false.B, EndBusy_d)
// Update MII RX_DATA register
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
// Generation of the delayed signals used for positive edge triggering.
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
// Generation of the Start Commands (Write Control Data or Read Status)
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
when( EndBusy ){
WCtrlDataStart := false.B
RStatStart := false.B
} .otherwise{
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
WCtrlDataStart := true.B
}
when(RStat_q(1) & ~RStat_q(2)){
RStatStart := true.B
}
}
// Generation of the Nvalid signal (indicates when the status is invalid)
val Nvalid = RegInit(false.B)
when( ~InProgress_q2 & InProgress_q3 ) {
Nvalid := false.B
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
Nvalid := true.B
}
// Signals used for the generation of the Operation signals (positive edge)
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
// Generation of the Operation signals
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
val InProgress = RegInit(false.B) // Operation in progress
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
when(MdcEn){
when(StartOp) {
InProgress := true.B
when( ~InProgress ){
WriteOp := WriteDataOp
}
} .elsewhen(EndOp) {
InProgress := false.B
WriteOp := false.B
}
}
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
when( MdcEn ){
when( InProgress ) {
when( NoPre & BitCounter === 0.U ) {
BitCounter := "h21".U
} .otherwise {
BitCounter := BitCounter + 1.U
}
} .otherwise {
BitCounter := 0.U
}
}
// Operation ends when the Bit Counter reaches 63
val EndOp = BitCounter === 63.U // End of Operation
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
!"#$! &XSET CREATE_BUILD 214" "
<0A>CREATE USER IF NOT EXISTS "SA" SALT '570c662a4aed13d7' HASH '684ffa8cfe9ed7d665d50297eddd3152fc77e49e35da93e6c9cefb0c5e3c2533' ADMIN#
<0A>CREATE CACHED TABLE "PUBLIC"."flyway_schema_history"(
"installed_rank" INTEGER NOT NULL,
"version" CHARACTER VARYING(50),
"description" CHARACTER VARYING(200) NOT NULL,
"type" CHARACTER VARYING(20) NOT NULL,
"script" CHARACTER VARYING(1000) NOT NULL,
"checksum" INTEGER,
"installed_by" CHARACTER VARYING(100) NOT NULL,
"installed_on" TIMESTAMP DEFAULT CURRENT_TIMESTAMP NOT NULL,
"execution_time" INTEGER NOT NULL,
"success" BOOLEAN NOT NULL
)$ !
aCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_6" ON "PUBLIC"."flyway_schema_history"("installed_rank")% %
<0A>ALTER TABLE "PUBLIC"."flyway_schema_history" ADD CONSTRAINT "PUBLIC"."flyway_schema_history_pk" PRIMARY KEY("installed_rank") INDEX "PUBLIC"."PRIMARY_KEY_6"& !
nCREATE INDEX "PUBLIC"."flyway_schema_history_s_idx" ON "PUBLIC"."flyway_schema_history"("success" NULLS FIRST)'
<0A>CREATE CACHED TABLE "PUBLIC"."DEPENDENCY_SOURCE"(
) !
[CREATE INDEX "PUBLIC"."CONSTRAINT_INDEX_3" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR" NULLS FIRST) %
<0A>ALTER TABLE "PUBLIC"."TOPLEVEL_SYMBOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_3" FOREIGN KEY("JAR") INDEX "PUBLIC"."CONSTRAINT_INDEX_3" REFERENCES "PUBLIC"."INDEXED_JAR"("ID") ON DELETE CASCADE NOCHECK !
bCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_3" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR", "PATH", "SYMBOL") %
<0A>ALTER TABLE "PUBLIC"."TOPLEVEL_SYMBOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_34" PRIMARY KEY("JAR", "PATH", "SYMBOL") INDEX "PUBLIC"."PRIMARY_KEY_3" !
\CREATE INDEX "PUBLIC"."TOPLEVEL_SYMBOL_JAR" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR" NULLS FIRST)!
<0A>CREATE CACHED TABLE "PUBLIC"."FINGERPRINTS"(
"PATH" CHARACTER VARYING NOT NULL,
"TEXT" CHARACTER VARYING NOT NULL,
"MD5" CHARACTER VARYING NOT NULL,
"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_D3048AD8_D59B_4EFB_8127_D20032B9687A" NOT NULL
)" #
<0A>CREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_D3048AD8_D59B_4EFB_8127_D20032B9687A" AS INTEGER START WITH 1 RESTART WITH 32 BELONGS_TO_TABLE# !
^CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_9" ON "PUBLIC"."FINGERPRINTS"("ID" NULLS FIRST)$ %
|ALTER TABLE "PUBLIC"."FINGERPRINTS" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9B" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_9"<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>AAAAABn
chunk.16chunk.17chunk.19chunk.1ameta.idroot.1root.2root.5root.broot.c<>chunk:16,block:2,len:2,liveMax:0,livePages:0,map:2e,max:1ab0,next:7,pages:6,root:58000048016,time:47a07d5,unused:8948386,unusedAtVersion:19,version:16,toc:1757,occupancy:3f<33>chunk:17,block:7,len:47,liveMax:0,livePages:0,map:2e,max:55d40,pages:13,root:5c001178614,time:47a07e3,unused:8948394,unusedAtVersion:1a,version:17,toc:46174,occupancy:ffff07<30>chunk:19,block:4,len:1,liveMax:0,livePages:0,map:30,max:e30,next:5,pages:4,root:64000025412,time:47a0a3d,unused:8948386,unusedAtVersion:19,version:19,toc:bd1,occupancy:0f<30>chunk:1a,block:5,len:2,liveMax:14b0,livePages:5,map:32,max:18b0,next:7,pages:6,root:6800004a1d4,time:8948386,unusedAtVersion:1a,version:1a,toc:15ca,occupancy:20168000027a0368000002c586c000002c5e6800002214e6c000054640@,^F@M<>ut [7:0] Divider; // Divider for the host clock
