15548 lines
612 KiB
Plaintext
15548 lines
612 KiB
Plaintext
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H:2,block:97,blockSize:1000,chunk:15,created:188cdd6b793,format:2,version:15,fletcher:8e9fa6f0
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H:2,block:97,blockSize:1000,chunk:15,created:188cdd6b793,format:2,version:15,fletcher:8e9fa6f0
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chunk:f,block:2,len:1,map:2a,max:580,pages:2,root:3c000008454,time:c18f8a,version:f,toc:525
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c<01> <00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> B
)<< Flyway Schema History table created >>ITABLED FSA ҝ?<3F><><EFBFBD>ȋ A!E1QCreate tablesGSQLYV1__Create_tables.sql<04>ױ<EFBFBD>FSA ҝ?<3F><><EFBFBD><10><>
(A"E2TServer discoveryGSQL\V2__Server_discovery.sqlB<6C><42><EFBFBD><EFBFBD>FSA ҝ?Ơ<><10><>,(A#E3OJar symbolsGSQLWV3__Jar_symbols.sqlBī<42><C4AB>FSA ҝ?頦ЉA$E4PFingerprintsGSQLXV4__Fingerprints.sqlߌ<>FSA ҝ?<3F><><EFBFBD>،#A
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chunk.bchunk.cchunk.dchunk.emeta.idroot.1root.2root.5root.broot.c<>chunk:b,block:9,len:4,liveMax:0,livePages:0,map:26,max:3c20,next:d,pages:4,root:2c0000ce5d4,time:7e73d8,unused:7fc4d1,unusedAtVersion:d,version:b,toc:36c8,occupancy:0f<30>chunk:c,block:d,len:2,liveMax:820,livePages:2,map:28,max:18d0,next:f,pages:7,root:300000442d4,time:7fc045,unusedAtVersion:e,version:c,toc:1507,occupancy:7a<37>chunk:d,block:f,len:1,liveMax:b30,livePages:3,map:2a,max:1130,next:10,pages:4,root:340000252d6,time:7fc2bc,unusedAtVersion:d,version:d,toc:dc4,occupancy:08<30>chunk:e,block:2,len:2,liveMax:1800,livePages:1,map:2a,max:1b00,next:4,pages:2,root:38000054552,time:7fc4d1,unusedAtVersion:e,version:e,toc:1783,occupancy:021 34000002b83 30000002b98 38000002b9e 3c000002b8e 30000021400 <02> +<2B> <00>TARACTER VARYING NOT NULL,
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"BUILD_TARGET_URI" CHARACTER VARYING NOT NULL
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)( !
`CREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_9" ON "PUBLIC"."DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI")) %
<0A>ALTER TABLE "PUBLIC"."DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_9"*
<0A>CREATE CACHED TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"(
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"TEXT_DOCUMENT_URI" CHARACTER VARYING NOT NULL,
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"WORKSHEET_URI" CHARACTER VARYING NOT NULL
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)+ !
jCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_F" ON "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI"), %
<0A>ALTER TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_F" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_F"-
<0A>CREATE CACHED TABLE "PUBLIC"."SBT_DIGEST"(
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"MD5" CHARACTER VARYING,
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"STATUS" TINYINT NOT NULL,
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"WHEN_RECORDED" TIMESTAMP
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).
<0A>CREATE CACHED TABLE "PUBLIC"."DISMISSED_NOTIFICATION"(
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"ID" INTEGER,
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"WHEN_DISMISSED" TIMESTAMP,
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"WHEN_EXPIRES" TIMESTAMP
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)/
_CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_TOOL"(
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"BUILD_TOOL" CHARACTER VARYING NOT NULL
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) !
ZCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_68" ON "PUBLIC"."CHOSEN_BUILD_TOOL"("BUILD_TOOL") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_TOOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_6" PRIMARY KEY("BUILD_TOOL") INDEX "PUBLIC"."PRIMARY_KEY_68"
<0A>CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_SERVER"(
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"MD5" CHARACTER VARYING NOT NULL,
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"SELECTED_SERVER" CHARACTER VARYING,
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"WHEN_RECORDED" TIMESTAMP
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) !
UCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_93" ON "PUBLIC"."CHOSEN_BUILD_SERVER"("MD5") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_SERVER" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_93" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_93"
<0A>CREATE CACHED TABLE "PUBLIC"."INDEXED_JAR"(
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"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" NOT NULL,
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"MD5" CHARACTER VARYING NOT NULL
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) #
xCREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" AS INTEGER START WITH 1 BELONGS_TO_TABLE !
]CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_E" ON "PUBLIC"."INDEXED_JAR"("ID" NULLS FIRST) %
zALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_E" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_E" !
LCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_E" ON "PUBLIC"."INDEXED_JAR"("MD5") %
|ALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_EE" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_E"
<0A>CREATE CACHED TABLE "PUBLIC"."TOPLEVEL_SYMBOL"(
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"SYMBchunk:f,block:2,version:f,fletcher:cbd23ff7
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chunk:d,block:3,len:1,map:2a,max:1130,pages:4,root:340000252d6,time:7fc2bc,version:d,toc:dc4
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" <00> @ 4 @ Πmap.f F<06> map.10map.11map.12map.13map.14map.15map.16map.17map.18map.19map.1amap.1bmap.1cmap.1dmap.1emap.1fmap.2map.20map.29map.2amap.3map.5map.6map.7map.8map.9map.bmap.cmap.e7name:table.10,createVersion:1,key:8fa25204,val:5eb2888f7name:index.11,createVersion:1,key:8b890ce3,val:da71dbdb7name:table.13,createVersion:1,key:8fa25204,val:5eaca19a7name:table.14,createVersion:1,key:8fa25204,val:5eaca19a7name:table.15,createVersion:1,key:8fa25204,val:5eb3a9587name:index.16,createVersion:1,key:8b889884,val:da71dbdb7name:table.18,createVersion:1,key:8fa25204,val:5eaca19a7name:index.19,createVersion:1,key:8b898142,val:da71dbdb7name:table.21,createVersion:1,key:8fa25204,val:5eb2888f7name:index.23,createVersion:1,key:8b890d13,val:da71dbdb7name:index.25,createVersion:1,key:8b891095,val:da71dbdb7name:table.27,createVersion:1,key:8fa25204,val:5eaca19a7name:index.28,createVersion:1,key:8b898902,val:da71dbdb7name:index.30,createVersion:1,key:8d68a4f4,val:da71dbdb7name:index.32,createVersion:1,key:8b898902,val:da71dbdb7name:table.33,createVersion:1,key:8fa25204,val:5803b3f1name:_7name:index.35,createVersion:1,key:8b8a011f,val:da71dbdb name:undoLog.1,createVersion:c name:undoLog.2,createVersion:cname:openTransactions&name:table.0,key:8fa25204,val:5803b3f1%name:lobMap,key:8fa25204,val:f4470498)name:tempLobMap,key:8fa25204,val:59a6a071$name:lobRef,key:eabe0274,val:f4a56b5&name:lobData,key:8fa25204,val:59a6a0716name:table.3,createVersion:1,key:8fa25204,val:f25aa7b76name:index.6,createVersion:1,key:8b8cd1e9,val:da71dbdb6name:table.7,createVersion:1,key:8fa25204,val:5eb2888f 5. map.fname._
name.index.11
name.index.16
name.index.19
name.index.23
name.index.25
name.index.28
name.index.30
name.index.32
name.index.35 name.index.6 name.index.8 name.lobData name.lobMap name.lobRefname.openTransactions name.table.0
name.table.10
name.table.13
name.table.14
name.table.15
name.table.18
name.table.21
name.table.27 name.table.3
name.table.33 name.table.7name.tempLobMapname.undoLog.1name.undoLog.26name:index.8,createVersion:1,key:8b890ce3,val:da71dbdb2111517191a1c1d1e20cf968351012131416181bb1fe7292a y
? chunk.5chunk.6chunk.9chunk.achunk.bchunk.cmeta.idroot.1root.2root.5root.broot.c<>chunk:5,block:2,len:2,liveMax:0,livePages:0,map:24,max:15b0,next:4,pages:6,root:14000041992,time:724d95,unused:7fc045,unusedAtVersion:b,version:5,toc:12d2,occupancy:3f<33>chunk:6,block:7,len:2,liveMax:0,livePages:0,map:24,max:1b20,pages:3,root:180000548d2,time:724dc8,unused:7fc045,unusedAtVersion:b,version:6,toc:1788,occupancy:07<30>chunk:9,block:4,len:1,liveMax:0,livePages:0,map:26,max:f30,next:5,pages:4,root:240000252d4,time:725048,unused:7fc045,unusedAtVersion:b,version:9,toc:c59,occupancy:0f<30>chunk:a,block:5,len:2,liveMax:0,livePages:0,map:26,max:1c00,next:b,pages:2,root:28000054594,time:7e73bb,unused:7e73d8,unusedAtVersion:a,version:a,toc:181d,occupancy:03<30>chunk:b,block:9,len:4,liveMax:1800,livePages:1,map:26,max:3c20,next:d,pages:4,root:2c0000ce5d4,time:7e73d8,unusedAtVersion:c,version:b,toc:36c8,occupancy:0e<30>chunk:c,block:d,len:2,liveMax:9a0,livePages:3,map:28,max:18d0,next:f,pages:7,root:300000442d4,time:7fc045,unusedAtVersion:c,version:c,toc:1507,occupancy:781 34000002b83 30000002b98 2c000002b9e 3000001bb4e 30000021400 @ +<2B> @ 4 @ ΠR<> chunk:d,block:3,version:d,fletcher:bbd23cf7
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chunk:11,block:4,len:3,map:2a,max:32d0,pages:8,root:44000095d56,time:c601e9,version:11,toc:298b
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?<06> 377d660d5803b3f159a6a0715eaca19a5eb2888f5eb3a95877cea3368b8898848b890ce38b890d138b8910958b8981428b8989028b8a011f8b8cd1e98d68a4f48fa25204a2f52e58da71dbdbe246eb63eabe0274f25aa7b7f4470498f4a56b5#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.type.ByteArrayDataType,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory ,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory ,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory #org.h2.mvstore.db.NullValueDataType%org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory%org.h2.mvstore.db.RowDataType$Factory%org.h2.mvstore.db.RowDataType$Factory
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%org.h2.mvstore.db.RowDataType$Factory org.h2.mvstore.type.LongDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType2org.h2.mvstore.db.LobStorageMap$BlobReference$Type,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory
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-org.h2.mvstore.db.LobStorageMap$BlobMeta$Type#org.h2.mvstore.db.NullValueDataType h<12>$
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!"#$ ! &XSET CREATE_BUILD 214" "
<0A>CREATE USER IF NOT EXISTS "SA" SALT '570c662a4aed13d7' HASH '684ffa8cfe9ed7d665d50297eddd3152fc77e49e35da93e6c9cefb0c5e3c2533' ADMIN#
<0A>CREATE CACHED TABLE "PUBLIC"."flyway_schema_history"(
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"installed_rank" INTEGER NOT NULL,
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"version" CHARACTER VARYING(50),
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"description" CHARACTER VARYING(200) NOT NULL,
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"type" CHARACTER VARYING(20) NOT NULL,
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"script" CHARACTER VARYING(1000) NOT NULL,
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"checksum" INTEGER,
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"installed_by" CHARACTER VARYING(100) NOT NULL,
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"installed_on" TIMESTAMP DEFAULT CURRENT_TIMESTAMP NOT NULL,
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"execution_time" INTEGER NOT NULL,
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"success" BOOLEAN NOT NULL
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)$ !
aCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_6" ON "PUBLIC"."flyway_schema_history"("installed_rank")% %
<0A>ALTER TABLE "PUBLIC"."flyway_schema_history" ADD CONSTRAINT "PUBLIC"."flyway_schema_history_pk" PRIMARY KEY("installed_rank") INDEX "PUBLIC"."PRIMARY_KEY_6"& !
nCREATE INDEX "PUBLIC"."flyway_schema_history_s_idx" ON "PUBLIC"."flyway_schema_history"("success" NULLS FIRST)'
<0A>CREATE CACHED TABLE "PUBLIC"."DEPENDENCY_SOURCE"(
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"TEXT_DOCUMENT_URI" CHARACTER VARYING NOT NULL,
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"BUILD_TARGET_URI" CHARACTER VARYING NOT NULL
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)( !
`CREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_9" ON "PUBLIC"."DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI")) %
<0A>ALTER TABLE "PUBLIC"."DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_9"*
<0A>CREATE CACHED TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"(
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"TEXT_DOCUMENT_URI" CHARACTER VARYING NOT NULL,
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"WORKSHEET_URI" CHARACTER VARYING NOT NULL
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)+ !
jCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_F" ON "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI"), %
<0A>ALTER TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_F" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_F"-
<0A>CREATE CACHED TABLE "PUBLIC"."SBT_DIGEST"(
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"MD5" CHARACTER VARYING,
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"STATUS" TINYINT NOT NULL,
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"WHEN_RECORDED" TIMESTAMP
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).
<0A>CREATE CACHED TABLE "PUBLIC"."DISMISSED_NOTIFICATION"(
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"ID" INTEGER,
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"WHEN_DISMISSED" TIMESTAMP,
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"WHEN_EXPIRES" TIMESTAMP
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)/
_CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_TOOL"(
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"BUILD_TOOL" CHARACTER VARYING NOT NULL
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) !
ZCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_68" ON "PUBLIC"."CHOSEN_BUILD_TOOL"("BUILD_TOOL") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_TOOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_6" PRIMARY KEY("BUILD_TOOL") INDEX "PUBLIC"."PRIMARY_KEY_68"
<0A>CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_SERVER"(
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"MD5" CHARACTER VARYING NOT NULL,
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"SELECTED_SERVER" CHARACTER VARYING,
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"WHEN_RECORDED" TIMESTAMP
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) !
UCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_93" ON "PUBLIC"."CHOSEN_BUILD_SERVER"("MD5") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_SERVER" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_93" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_93"
<0A>CREATE CACHED TABLE "PUBLIC"."INDEXED_JAR"(
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"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" NOT NULL,
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"MD5" CHARACTER VARYING NOT NULL
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) #
xCREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" AS INTEGER START WITH 1 BELONGS_TO_TABLE !
]CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_E" ON "PUBLIC"."INDEXED_JAR"("ID" NULLS FIRST) %
zALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_E" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_E" !
LCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_E" ON "PUBLIC"."INDEXED_JAR"("MD5") %
|ALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_EE" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_E"
<0A>CREATE CACHED TABLE "PUBLIC"."TOPLEVEL_SYMBOL"(
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"SYMBOL" CHARACTER VARYING NOT NULL,
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"PATH" CHARACTER VARYING NOT NULL,
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"JAR" INTEGER NOT NULL
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) !
[CREATE INDEX "PUBLIC"."CONSTRAINT_INDEX_3" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR" NULLS FIRST) %
<0A>ALTER TABLE "PUBLIC"."TOPLEVEL_SYMBOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_3" FOREIGN KEY("JAR") INDEX "PUBLIC"."CONSTRAINT_INDEX_3" REFERENCES "PUBLIC"."INDEXED_JAR"("ID") ON DELETE CASCADE NOCHECK !
bCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_3" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR", "PATH", "SYMBOL") %
<0A>ALTER TABLE "PUBLIC"."TOPLEVEL_SYMBOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_34" PRIMARY KEY("JAR", "PATH", "SYMBOL") INDEX "PUBLIC"."PRIMARY_KEY_3" !
\CREATE INDEX "PUBLIC"."TOPLEVEL_SYMBOL_JAR" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR" NULLS FIRST)!
<0A>CREATE CACHED TABLE "PUBLIC"."FINGERPRINTS"(
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"PATH" CHARACTER VARYING NOT NULL,
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"TEXT" CHARACTER VARYING NOT NULL,
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"MD5" CHARACTER VARYING NOT NULL,
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"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_D3048AD8_D59B_4EFB_8127_D20032B9687A" NOT NULL
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)" #
<0A>CREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_D3048AD8_D59B_4EFB_8127_D20032B9687A" AS INTEGER START WITH 1 RESTART WITH 32 BELONGS_TO_TABLE# !
^CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_9" ON "PUBLIC"."FINGERPRINTS"("ID" NULLS FIRST)$ %
|ALTER TABLE "PUBLIC"."FINGERPRINTS" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9B" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_9" c% <00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> B
)<< Flyway Schema History table created >>ITABLED FSA ҝ?<3F><><EFBFBD>ȋ A!E1QCreate tablesGSQLYV1__Create_tables.sql<04>ױ<EFBFBD>FSA ҝ?<3F><><EFBFBD><10><>
(A"E2TServer discoveryGSQL\V2__Server_discovery.sqlB<6C><42><EFBFBD><EFBFBD>FSA ҝ?Ơ<><10><>,(A#E3OJar symbolsGSQLWV3__Jar_symbols.sqlBī<42><C4AB>FSA ҝ?頦ЉA$E4PFingerprintsGSQLXV4__Fingerprints.sqlߌ<>FSA ҝ?<3F><><EFBFBD>،#A <1C> <00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>AAAAA " <1C> @ ><3E> @ <08> map.f F<1A> map.10map.11map.12map.13map.14map.15map.16map.17map.18map.19map.1amap.1bmap.1cmap.1dmap.1emap.1fmap.2map.20map.29map.2amap.3map.5map.6map.7map.8map.9map.bmap.cmap.e7name:table.10,createVersion:1,key:8fa25204,val:5eb2888f7name:index.11,createVersion:1,key:8b890ce3,val:da71dbdb7name:table.13,createVersion:1,key:8fa25204,val:5eaca19a7name:table.14,createVersion:1,key:8fa25204,val:5eaca19a7name:table.15,createVersion:1,key:8fa25204,val:5eb3a9587name:index.16,createVersion:1,key:8b889884,val:da71dbdb7name:table.18,createVersion:1,key:8fa25204,val:5eaca19a7name:index.19,createVersion:1,key:8b898142,val:da71dbdb7name:table.21,createVersion:1,key:8fa25204,val:5eb2888f7name:index.23,createVersion:1,key:8b890d13,val:da71dbdb7name:index.25,createVersion:1,key:8b891095,val:da71dbdb7name:table.27,createVersion:1,key:8fa25204,val:5eaca19a7name:index.28,createVersion:1,key:8b898902,val:da71dbdb7name:index.30,createVersion:1,key:8d68a4f4,val:da71dbdb7name:index.32,createVersion:1,key:8b898902,val:da71dbdb7name:table.33,createVersion:1,key:8fa25204,val:5803b3f1name:_7name:index.35,createVersion:1,key:8b8a011f,val:da71dbdb name:undoLog.1,createVersion:c name:undoLog.2,createVersion:cname:openTransactions&name:table.0,key:8fa25204,val:5803b3f1%name:lobMap,key:8fa25204,val:f4470498)name:tempLobMap,key:8fa25204,val:59a6a071$name:lobRef,key:eabe0274,val:f4a56b5&name:lobData,key:8fa25204,val:59a6a0716name:table.3,createVersion:1,key:8fa25204,val:f25aa7b76name:index.6,createVersion:1,key:8b8cd1e9,val:da71dbdb6name:table.7,createVersion:1,key:8fa25204,val:5eb2888f 5!d map.fname._
name.index.11
name.index.16
name.index.19
name.index.23
name.index.25
name.index.28
name.index.30
name.index.32
name.index.35 name.index.6 name.index.8 name.lobData name.lobMap name.lobRefname.openTransactions name.table.0
name.table.10
name.table.13
name.table.14
name.table.15
name.table.18
name.table.21
name.table.27 name.table.3
name.table.33 name.table.7name.tempLobMapname.undoLog.1name.undoLog.26name:index.8,createVersion:1,key:8b890ce3,val:da71dbdb2111517191a1c1d1e20cf968351012131416181bb1fe7292a !r
chunk.10chunk.cchunk.dchunk.echunk.fmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:10,block:10,len:47,liveMax:54120,livePages:10,map:2a,max:55d20,next:57,pages:12,root:40001177e54,time:c60122,unusedAtVersion:10,version:10,toc:46132,occupancy:010002<30>chunk:c,block:d,len:2,liveMax:0,livePages:0,map:28,max:18d0,next:f,pages:7,root:300000442d4,time:7fc045,unused:c601e9,unusedAtVersion:10,version:c,toc:1507,occupancy:7f<37>chunk:d,block:f,len:1,liveMax:0,livePages:0,map:2a,max:1130,next:10,pages:4,root:340000252d6,time:7fc2bc,unused:c601e9,unusedAtVersion:10,version:d,toc:dc4,occupancy:0f<30>chunk:e,block:2,len:2,liveMax:0,livePages:0,map:2a,max:1b00,next:4,pages:2,root:38000054552,time:7fc4d1,unused:c60122,unusedAtVersion:f,version:e,toc:1783,occupancy:03<30>chunk:f,block:4,len:1,liveMax:0,livePages:0,map:2a,max:580,next:5,pages:2,root:3c000008454,time:c18f8a,unused:c601e9,unusedAtVersion:10,version:f,toc:525,occupancy:031 44000073603 4000005460b 44000002c18 40001176886 4400001bbde 4400006d5ce 44000072e80 <00> , @ <01><> <02> <06><> .<2E> @ 6 @ ><3E> @ <08> ]VataOp = WCtrlDataSta
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
Bichunk:11,block:4,version:11,fletcher:90098ba5
|
|||
|
|
chunk:c,block:7,len:2,map:28,max:18d0,pages:7,root:300000442d4,time:7fc045,version:c,toc:1507
|
|||
|
|
?<06> 377d660d5803b3f159a6a0715eaca19a5eb2888f5eb3a95877cea3368b8898848b890ce38b890d138b8910958b8981428b8989028b8a011f8b8cd1e98d68a4f48fa25204a2f52e58da71dbdbe246eb63eabe0274f25aa7b7f4470498f4a56b5#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.type.ByteArrayDataType,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory ,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory ,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory #org.h2.mvstore.db.NullValueDataType%org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory%org.h2.mvstore.db.RowDataType$Factory%org.h2.mvstore.db.RowDataType$Factory
|
|||
|
|
%org.h2.mvstore.db.RowDataType$Factory org.h2.mvstore.type.LongDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType2org.h2.mvstore.db.LobStorageMap$BlobReference$Type,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory
|
|||
|
|
-org.h2.mvstore.db.LobStorageMap$BlobMeta$Type#org.h2.mvstore.db.NullValueDataType c<07> <00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> B
)<< Flyway Schema History table created >>ITABLED FSA ҝ?<3F><><EFBFBD>ȋ A!E1QCreate tablesGSQLYV1__Create_tables.sql<04>ױ<EFBFBD>FSA ҝ?<3F><><EFBFBD><10><>
(A"E2TServer discoveryGSQL\V2__Server_discovery.sqlB<6C><42><EFBFBD><EFBFBD>FSA ҝ?Ơ<><10><>,(A#E3OJar symbolsGSQLWV3__Jar_symbols.sqlBī<42><C4AB>FSA ҝ?頦ЉA$E4PFingerprintsGSQLXV4__Fingerprints.sqlߌ<>FSA ҝ?<3F><><EFBFBD>،#A B <00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>AAAAA "@ $ <03><> map.f F<0E> map.10map.11map.12map.13map.14map.15map.16map.17map.18map.19map.1amap.1bmap.1cmap.1dmap.1emap.1fmap.2map.20map.27map.28map.3map.5map.6map.7map.8map.9map.bmap.cmap.e7name:table.10,createVersion:1,key:8fa25204,val:5eb2888f7name:index.11,createVersion:1,key:8b890ce3,val:da71dbdb7name:table.13,createVersion:1,key:8fa25204,val:5eaca19a7name:table.14,createVersion:1,key:8fa25204,val:5eaca19a7name:table.15,createVersion:1,key:8fa25204,val:5eb3a9587name:index.16,createVersion:1,key:8b889884,val:da71dbdb7name:table.18,createVersion:1,key:8fa25204,val:5eaca19a7name:index.19,createVersion:1,key:8b898142,val:da71dbdb7name:table.21,createVersion:1,key:8fa25204,val:5eb2888f7name:index.23,createVersion:1,key:8b890d13,val:da71dbdb7name:index.25,createVersion:1,key:8b891095,val:da71dbdb7name:table.27,createVersion:1,key:8fa25204,val:5eaca19a7name:index.28,createVersion:1,key:8b898902,val:da71dbdb7name:index.30,createVersion:1,key:8d68a4f4,val:da71dbdb7name:index.32,createVersion:1,key:8b898902,val:da71dbdb7name:table.33,createVersion:1,key:8fa25204,val:5803b3f1name:_7name:index.35,createVersion:1,key:8b8a011f,val:da71dbdb name:undoLog.1,createVersion:b name:undoLog.2,createVersion:bname:openTransactions&name:table.0,key:8fa25204,val:5803b3f1%name:lobMap,key:8fa25204,val:f4470498)name:tempLobMap,key:8fa25204,val:59a6a071$name:lobRef,key:eabe0274,val:f4a56b5&name:lobData,key:8fa25204,val:59a6a0716name:table.3,createVersion:1,key:8fa25204,val:f25aa7b76name:index.6,createVersion:1,key:8b8cd1e9,val:da71dbdb6name:table.7,createVersion:1,key:8fa25204,val:5eb2888f 5 <0C> map.fname._
name.index.11
name.index.16
name.index.19
name.index.23
name.index.25
name.index.28
name.index.30
name.index.32
name.index.35 name.index.6 name.index.8 name.lobData name.lobMap name.lobRefname.openTransactions name.table.0
name.table.10
name.table.13
name.table.14
name.table.15
name.table.18
name.table.21
name.table.27 name.table.3
name.table.33 name.table.7name.tempLobMapname.undoLog.1name.undoLog.26name:index.8,createVersion:1,key:8b890ce3,val:da71dbdb2111517191a1c1d1e20cf968351012131416181bb1fe72728 <03><12>
chunk.5chunk.6chunk.9chunk.achunk.bmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:5,block:2,len:2,liveMax:0,livePages:0,map:24,max:15b0,next:4,pages:6,root:14000041992,time:724d95,unused:7fc045,unusedAtVersion:b,version:5,toc:12d2,occupancy:3f<33>chunk:6,block:7,len:2,liveMax:0,livePages:0,map:24,max:1b20,pages:3,root:180000548d2,time:724dc8,unused:7fc045,unusedAtVersion:b,version:6,toc:1788,occupancy:07<30>chunk:9,block:4,len:1,liveMax:0,livePages:0,map:26,max:f30,next:5,pages:4,root:240000252d4,time:725048,unused:7fc045,unusedAtVersion:b,version:9,toc:c59,occupancy:0f<30>chunk:a,block:5,len:2,liveMax:0,livePages:0,map:26,max:1c00,next:b,pages:2,root:28000054594,time:7e73bb,unused:7e73d8,unusedAtVersion:a,version:a,toc:181d,occupancy:03<30>chunk:b,block:9,len:4,liveMax:3820,livePages:3,map:26,max:3c20,next:d,pages:4,root:2c0000ce5d4,time:7e73d8,unusedAtVersion:b,version:b,toc:36c8,occupancy:081 30000021b83 2c000054560 30000002b98 2c0000ce280 2c000002b9e 3000001bb4e 30000021400 <00> +<2B> <02> <01>N @ <1B> @ $ @ <03><> B<>
|
|||
|
|
chunk:10,block:9,len:47,map:2a,max:55d20,pages:12,root:40001177e54,time:c60122,version:10,toc:46132
|
|||
|
|
h<14> $
|
|||
|
|
!"#$ ! &XSET CREATE_BUILD 214" "
<0A>CREATE USER IF NOT EXISTS "SA" SALT '570c662a4aed13d7' HASH '684ffa8cfe9ed7d665d50297eddd3152fc77e49e35da93e6c9cefb0c5e3c2533' ADMIN#
<0A>CREATE CACHED TABLE "PUBLIC"."flyway_schema_history"(
|
|||
|
|
"installed_rank" INTEGER NOT NULL,
|
|||
|
|
"version" CHARACTER VARYING(50),
|
|||
|
|
"description" CHARACTER VARYING(200) NOT NULL,
|
|||
|
|
"type" CHARACTER VARYING(20) NOT NULL,
|
|||
|
|
"script" CHARACTER VARYING(1000) NOT NULL,
|
|||
|
|
"checksum" INTEGER,
|
|||
|
|
"installed_by" CHARACTER VARYING(100) NOT NULL,
|
|||
|
|
"installed_on" TIMESTAMP DEFAULT CURRENT_TIMESTAMP NOT NULL,
|
|||
|
|
"execution_time" INTEGER NOT NULL,
|
|||
|
|
"success" BOOLEAN NOT NULL
|
|||
|
|
)$ !
aCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_6" ON "PUBLIC"."flyway_schema_history"("installed_rank")% %
<0A>ALTER TABLE "PUBLIC"."flyway_schema_history" ADD CONSTRAINT "PUBLIC"."flyway_schema_history_pk" PRIMARY KEY("installed_rank") INDEX "PUBLIC"."PRIMARY_KEY_6"& !
nCREATE INDEX "PUBLIC"."flyway_schema_history_s_idx" ON "PUBLIC"."flyway_schema_history"("success" NULLS FIRST)'
<0A>CREATE CACHED TABLE "PUBLIC"."DEPENDENCY_SOURCE"(
|
|||
|
|
"TEXT_DOCUMENT_URI" CHARACTER VARYING NOT NULL,
|
|||
|
|
"BUILD_TARGET_URI" CHARACTER VARYING NOT NULL
|
|||
|
|
)( !
`CREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_9" ON "PUBLIC"."DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI")) %
<0A>ALTER TABLE "PUBLIC"."DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_9"*
<0A>CREATE CACHED TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"(
|
|||
|
|
"TEXT_DOCUMENT_URI" CHARACTER VARYING NOT NULL,
|
|||
|
|
"WORKSHEET_URI" CHARACTER VARYING NOT NULL
|
|||
|
|
)+ !
jCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_F" ON "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI"), %
<0A>ALTER TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_F" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_F"-
<0A>CREATE CACHED TABLE "PUBLIC"."SBT_DIGEST"(
|
|||
|
|
"MD5" CHARACTER VARYING,
|
|||
|
|
"STATUS" TINYINT NOT NULL,
|
|||
|
|
"WHEN_RECORDED" TIMESTAMP
|
|||
|
|
).
<0A>CREATE CACHED TABLE "PUBLIC"."DISMISSED_NOTIFICATION"(
|
|||
|
|
"ID" INTEGER,
|
|||
|
|
"WHEN_DISMISSED" TIMESTAMP,
|
|||
|
|
"WHEN_EXPIRES" TIMESTAMP
|
|||
|
|
)/
_CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_TOOL"(
|
|||
|
|
"BUILD_TOOL" CHARACTER VARYING NOT NULL
|
|||
|
|
) !
ZCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_68" ON "PUBLIC"."CHOSEN_BUILD_TOOL"("BUILD_TOOL") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_TOOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_6" PRIMARY KEY("BUILD_TOOL") INDEX "PUBLIC"."PRIMARY_KEY_68"
<0A>CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_SERVER"(
|
|||
|
|
"MD5" CHARACTER VARYING NOT NULL,
|
|||
|
|
"SELECTED_SERVER" CHARACTER VARYING,
|
|||
|
|
"WHEN_RECORDED" TIMESTAMP
|
|||
|
|
) !
UCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_93" ON "PUBLIC"."CHOSEN_BUILD_SERVER"("MD5") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_SERVER" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_93" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_93"
<0A>CREATE CACHED TABLE "PUBLIC"."INDEXED_JAR"(
|
|||
|
|
"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" NOT NULL,
|
|||
|
|
"MD5" CHARACTER VARYING NOT NULL
|
|||
|
|
) #
xCREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" AS INTEGER START WITH 1 BELONGS_TO_TABLE !
]CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_E" ON "PUBLIC"."INDEXED_JAR"("ID" NULLS FIRST) %
zALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_E" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_E" !
LCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_E" ON "PUBLIC"."INDEXED_JAR"("MD5") %
|ALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_EE" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_E"
<0A>CREATE CACHED TABLE "PUBLIC"."TOPLEVEL_SYMBOL"(
|
|||
|
|
"SYMBOL" CHARACTER VARYING NOT NULL,
|
|||
|
|
"PATH" CHARACTER VARYING NOT NULL,
|
|||
|
|
"JAR" INTEGER NOT NULL
|
|||
|
|
) !
[CREATE INDEX "PUBLIC"."CONSTRAINT_INDEX_3" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR" NULLS FIRST) %
<0A>ALTER TABLE "PUBLIC"."TOPLEVEL_SYMBOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_3" FOREIGN KEY("JAR") INDEX "PUBLIC"."CONSTRAINT_INDEX_3" REFERENCES "PUBLIC"."INDEXED_JAR"("ID") ON DELETE CASCADE NOCHECK !
bCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_3" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR", "PATH", "SYMBOL") %
<0A>ALTER TABLE "PUBLIC"."TOPLEVEL_SYMBOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_34" PRIMARY KEY("JAR", "PATH", "SYMBOL") INDEX "PUBLIC"."PRIMARY_KEY_3" !
\CREATE INDEX "PUBLIC"."TOPLEVEL_SYMBOL_JAR" ON "PUBLIC"."TOPLEVEL_SYMBOL"("JAR" NULLS FIRST)!
<0A>CREATE CACHED TABLE "PUBLIC"."FINGERPRINTS"(
|
|||
|
|
"PATH" CHARACTER VARYING NOT NULL,
|
|||
|
|
"TEXT" CHARACTER VARYING NOT NULL,
|
|||
|
|
"MD5" CHARACTER VARYING NOT NULL,
|
|||
|
|
"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_D3048AD8_D59B_4EFB_8127_D20032B9687A" NOT NULL
|
|||
|
|
)" #
<0A>CREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_D3048AD8_D59B_4EFB_8127_D20032B9687A" AS INTEGER START WITH 1 RESTART WITH 34 BELONGS_TO_TABLE# !
^CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_9" ON "PUBLIC"."FINGERPRINTS"("ID" NULLS FIRST)$ %
|ALTER TABLE "PUBLIC"."FINGERPRINTS" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9B" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_9" <00><15>
kd <14><> '<27><> 9<>f Kw<4B> [<5B><> l<><6C> <00><>& <00>7& <00>|& <00><>f <00><07> <00>M<EFBFBD> <00><>(
=<3D>(
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MAC.scala
<0A>package MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MACBase extends Module {
|
|||
|
|
|
|||
|
|
class MACIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
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|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
7CA9882073A514DD01DF3046BE093A8F"
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A><package MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D0AC3A53A737689287208CFF922A712F#
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A><package MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D0AC3A53A737689287208CFF922A712F$ J<><19>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ipackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Wire(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
reg Mdc;
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Counter[7:0] <= 8'h1;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
begin
|
|||
|
|
Counter[7:0] <= CounterPreset[7:0];
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
Counter[7:0] <= Counter - 8'h1;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Mdc <= 1'b0;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
Mdc <= ~Mdc;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign CountEq0 = Counter == 8'h0;
|
|||
|
|
assign MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
assign MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
B9632DD2069E2A36F8DBB5D818704D2A%
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Jpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
val Counter = RegInit( 1.U(7.W) )
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
reg Mdc;
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Counter[7:0] <= 8'h1;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
begin
|
|||
|
|
Counter[7:0] <= CounterPreset[7:0];
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
Counter[7:0] <= Counter - 8'h1;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Mdc <= 1'b0;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
Mdc <= ~Mdc;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign CountEq0 = Counter == 8'h0;
|
|||
|
|
assign MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
assign MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
5869C959B2F7B69B374FA69D8A65D027& I<><49><EFBFBD>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ipackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
val Mdc = RegInit(false.B)
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Mdc <= 1'b0;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
Mdc <= ~Mdc;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign CountEq0 = Counter == 8'h0;
|
|||
|
|
assign MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
assign MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
69355A28E6FA5D795A15124EC0444153'
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Hpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
val Mdc = RegInit(false.B)
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
0823B26F5671228D3486B5AC445441A9( E<><45>
|
|||
|
|
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Gpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool())
|
|||
|
|
val MdcEn = Wire(Bool())
|
|||
|
|
val MdcEn_n = Wire(Bool())
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
FA647E951B06401024CF35E3773EBAF2)
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Bpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
F8AB5FC5483E7A72A4466DA6EF2F1268* Bo<>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MACBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
F59C771AB4E0025F5D6F25E02A0050A4+
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: MACBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
9BE813A4BCA6824B13550221B17E45DE, B%-<2D>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
ED7D77B71BE8FC3C4AC656872990DDAD-
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
9AFD0DD23373DA3409CD63188718F6A8. U<><55><EFBFBD>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ypackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
|||
|
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
|||
|
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
|||
|
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
|||
|
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
|||
|
|
endcase // case (ByteSelect[3:0])
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(LatchByte[0]){
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
always @ (posedge Clk or posedge Reset) begin
|
|||
|
|
if(Reset) begin
|
|||
|
|
ShiftReg[7:0] <= 8'h0;
|
|||
|
|
Prsd[15:0] <= 16'h0;
|
|||
|
|
LinkFail <= 1'b0;
|
|||
|
|
end else begin
|
|||
|
|
if(MdcEn_n) begin
|
|||
|
|
if(|ByteSelect) begin
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
|||
|
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
|||
|
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
|||
|
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
|||
|
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
|||
|
|
endcase // case (ByteSelect[3:0])
|
|||
|
|
/* verilator lint_on CASEINCOMPLETE */
|
|||
|
|
end else begin
|
|||
|
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
if(LatchByte[0]) begin
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
if(Rgad == 5'h01)
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
end else begin
|
|||
|
|
if(LatchByte[1])
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
610CCAA496FCB031A5030DE42047CBBF/
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(LatchByte[0]){
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
02C03E4689AD964763F5479A470D8C87 P<>W
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte[0]){
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
B56F227A545D2410BAB2A2E43825ECF3
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
508D70D451D054C8B6825C4A57FB5ADD Q <09>
|
|||
|
|
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail <= ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D5FAECA73D1FF939D74AA55086413D83
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
ACDF4A199C119563A2B4A1BAAF6D250F Q<19><>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte.extract(1)){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
7523BB18B49EE6BE7670C342F9B8C968
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd <= {ShiftReg(6:0), Mdi, Prsd(7,0)};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
DB1461EFA2DA25B6BD9C10FD3CDEB7BF Q<15>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
17AEF765ECF281E160C6D8FC41CC3CD3
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7);
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
C532740223E8669D42E1F2585F50DDB0 Q
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7)
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
901853399035F923273ED2159A07865F
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D35F9A0ED192B5EE763CCAE3EAFF641F M<>Я
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Dpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
F7A6846C1464BA401E14A3394F7F4047
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Tpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input InProgress; // Operation in progress
|
|||
|
|
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
input [6:0] BitCounter; // Bit Counter
|
|||
|
|
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
output Mdo; // MII Management Data Output
|
|||
|
|
output MdoEn; // MII Management Data Output Enable
|
|||
|
|
|
|||
|
|
wire SerialEn;
|
|||
|
|
|
|||
|
|
reg MdoEn_2d;
|
|||
|
|
reg MdoEn_d;
|
|||
|
|
reg MdoEn;
|
|||
|
|
|
|||
|
|
reg Mdo_2d;
|
|||
|
|
reg Mdo_d;
|
|||
|
|
reg Mdo; // MII Management Data Output
|
|||
|
|
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Mdo signal.
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= 1'b0;
|
|||
|
|
Mdo_d <= 1'b0;
|
|||
|
|
Mdo <= 1'b0;
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(MdcEn_n)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= ~SerialEn & BitCounter<32;
|
|||
|
|
Mdo_d <= ShiftedBit | Mdo_2d;
|
|||
|
|
Mdo <= Mdo_d;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
19C3E34B90072569B36126BE14BFC1FD r<><72>1
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Tpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input InProgress; // Operation in progress
|
|||
|
|
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
input [6:0] BitCounter; // Bit Counter
|
|||
|
|
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
output Mdo; // MII Management Data Output
|
|||
|
|
output MdoEn; // MII Management Data Output Enable
|
|||
|
|
|
|||
|
|
wire SerialEn;
|
|||
|
|
|
|||
|
|
reg MdoEn_2d;
|
|||
|
|
reg MdoEn_d;
|
|||
|
|
reg MdoEn;
|
|||
|
|
|
|||
|
|
reg Mdo_2d;
|
|||
|
|
reg Mdo_d;
|
|||
|
|
reg Mdo; // MII Management Data Output
|
|||
|
|
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Mdo signal.
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= 1'b0;
|
|||
|
|
Mdo_d <= 1'b0;
|
|||
|
|
Mdo <= 1'b0;
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(MdcEn_n)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= ~SerialEn & BitCounter<32;
|
|||
|
|
Mdo_d <= ShiftedBit | Mdo_2d;
|
|||
|
|
Mdo <= Mdo_d;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
19C3E34B90072569B36126BE14BFC1FD
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Gpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
val SerialEn = WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & NoPre ))
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
}
A01F248A627C8354F09F9FFE36732D98
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Gpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MDIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends MDIO{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
val SerialEn = WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & NoPre ))
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
}
59287D518069D400D6FD3CB7C9FB943D W]<5D> "#$%&'( )
|
|||
|
|
* + ,
-./ 9^<5E> chunk.cchunk.dchunk.echunk.fmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:c,block:d,len:2,liveMax:820,livePages:2,map:28,max:18d0,next:f,pages:7,root:300000442d4,time:7fc045,unusedAtVersion:e,version:c,toc:1507,occupancy:7a<37>chunk:d,block:f,len:1,liveMax:b30,livePages:3,map:2a,max:1130,next:10,pages:4,root:340000252d6,time:7fc2bc,unusedAtVersion:d,version:d,toc:dc4,occupancy:08<30>chunk:e,block:2,len:2,liveMax:0,livePages:0,map:2a,max:1b00,next:4,pages:2,root:38000054552,time:7fc4d1,unused:c60122,unusedAtVersion:f,version:e,toc:1783,occupancy:03<30>chunk:f,block:4,len:1,liveMax:180,livePages:1,map:2a,max:580,next:5,pages:2,root:3c000008454,time:c18f8a,unusedAtVersion:f,version:f,toc:525,occupancy:021 34000002b83 4000005460b 30000002b98 40001176886 40000002c1e 3c000002b8e 30000021400 @ , <07> F <07> kd <07> <14><> <07> '<27><> <07> 9<>f <07> Kw<4B> <07> [<5B><> <07> l<><6C> <07> <00><>& <07> <00>7& <07> <00>|& <07> <00><>f <07> <00><07> <07> <00>M<EFBFBD> <07> <00><>( h<> ~T
|
|||
|
|
chunk:13,block:50,len:1,map:2a,max:600,next:51,pages:1,root:4c000002c16,time:c6021b,version:13,toc:557
|
|||
|
|
<04> chunk.10chunk.11chunk.12chunk.cchunk.dchunk.fmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:10,block:9,len:47,liveMax:0,livePages:0,map:2a,max:55d20,pages:12,root:40001177e54,time:c60122,unused:c60208,unusedAtVersion:11,version:10,toc:46132,occupancy:ffff03<30>chunk:11,block:4,len:3,liveMax:2cd0,livePages:7,map:2a,max:32d0,pages:8,root:44000095d56,time:c601e9,unusedAtVersion:11,version:11,toc:298b,occupancy:80<38>chunk:12,block:a3,len:45,liveMax:54120,livePages:10,map:2a,max:54520,next:4,pages:11,root:48001126454,time:c60208,unusedAtVersion:12,version:12,toc:44d86,occupancy:000001<30>chunk:c,block:7,len:2,liveMax:0,livePages:0,map:28,max:18d0,pages:7,root:300000442d4,time:7fc045,unused:c601e9,unusedAtVersion:10,version:c,toc:1507,occupancy:7f<37>chunk:d,block:3,len:1,liveMax:0,livePages:0,map:2a,max:1130,pages:4,root:340000252d6,time:7fc2bc,unused:c601e9,unusedAtVersion:10,version:d,toc:dc4,occupancy:0f<30>chunk:f,block:2,len:1,liveMax:0,livePages:0,map:2a,max:580,pages:2,root:3c000008454,time:c18f8a,unused:c601e9,unusedAtVersion:10,version:f,toc:525,occupancy:031 44000073603 48000002c0b 44000002c18 48001124e86 4400001bbde 4400006d5ce 44000072e80 ,GET_URI" CHARACTER VARYING NOT NULL
|
|||
|
|
)( !
`CREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_9" ON "PUBLIC"."DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI")) %
<0A>ALTER TABLE "PUBLIC"."DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_9" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_9"*
<0A>CREATE CACHED TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"(
|
|||
|
|
"TEXT_DOCUMENT_URI" CHARACTER VARYING NOT NULL,
|
|||
|
|
"WORKSHEET_URI" CHARACTER VARYING NOT NULL
|
|||
|
|
)+ !
jCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_F" ON "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE"("TEXT_DOCUMENT_URI"), %
<0A>ALTER TABLE "PUBLIC"."WORKSHEET_DEPENDENCY_SOURCE" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_F" PRIMARY KEY("TEXT_DOCUMENT_URI") INDEX "PUBLIC"."PRIMARY_KEY_F"-
<0A>CREATE CACHED TABLE "PUBLIC"."SBT_DIGEST"(
|
|||
|
|
"MD5" CHARACTER VARYING,
|
|||
|
|
"STATUS" TINYINT NOT NULL,
|
|||
|
|
"WHEN_RECORDED" TIMESTAMP
|
|||
|
|
).
<0A>CREATE CACHED TABLE "PUBLIC"."DISMISSED_NOTIFICATION"(
|
|||
|
|
"ID" INTEGER,
|
|||
|
|
"WHEN_DISMISSED" TIMESTAMP,
|
|||
|
|
"WHEN_EXPIRES" TIMESTAMP
|
|||
|
|
)/
_CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_TOOL"(
|
|||
|
|
"BUILD_TOOL" CHARACTER VARYING NOT NULL
|
|||
|
|
) !
ZCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_68" ON "PUBLIC"."CHOSEN_BUILD_TOOL"("BUILD_TOOL") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_TOOL" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_6" PRIMARY KEY("BUILD_TOOL") INDEX "PUBLIC"."PRIMARY_KEY_68"
<0A>CREATE CACHED TABLE "PUBLIC"."CHOSEN_BUILD_SERVER"(
|
|||
|
|
"MD5" CHARACTER VARYING NOT NULL,
|
|||
|
|
"SELECTED_SERVER" CHARACTER VARYING,
|
|||
|
|
"WHEN_RECORDED" TIMESTAMP
|
|||
|
|
) !
UCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_93" ON "PUBLIC"."CHOSEN_BUILD_SERVER"("MD5") %
<0A>ALTER TABLE "PUBLIC"."CHOSEN_BUILD_SERVER" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_93" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_93"
<0A>CREATE CACHED TABLE "PUBLIC"."INDEXED_JAR"(
|
|||
|
|
"ID" INTEGER GENERATED BY DEFAULT AS IDENTITY SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" NOT NULL,
|
|||
|
|
"MD5" CHARACTER VARYING NOT NULL
|
|||
|
|
) #
xCREATE SEQUENCE "PUBLIC"."SYSTEM_SEQUENCE_312288EB_5267_423A_B74E_F29EAB338D41" AS INTEGER START WITH 1 BELONGS_TO_TABLE !
]CREATE UNIQUE INDEX "PUBLIC"."CONSTRAINT_INDEX_E" ON "PUBLIC"."INDEXED_JAR"("ID" NULLS FIRST) %
zALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_E" UNIQUE("ID") INDEX "PUBLIC"."CONSTRAINT_INDEX_E" !
LCREATE PRIMARY KEY "PUBLIC"."PRIMARY_KEY_E" ON "PUBLIC"."INDEXED_JAR"("MD5") %
|ALTER TABLE "PUBLIC"."INDEXED_JAR" ADD CONSTRAINT "PUBLIC"."CONSTRAINT_EE" PRIMARY KEY("MD5") INDEX "PUBLIC"."PRIMARY_KEY_E"
<0A>CREATE CACHED TABLE "PUBLIC"."TOPLEVEL_SYMBOL"(
|
|||
|
|
"SYchunk:13,block:50,version:13,fletcher:4d9acd98
|
|||
|
|
chunk:12,block:51,len:45,map:2a,max:54520,pages:11,root:48001126454,time:c60208,version:12,toc:44d86
|
|||
|
|
<00> 7
<04> Qd <04> <0F><> <04> "}<7D> <04> 4<>f <04> F]<5D> <04> V<><56> <04> gm<67> <04> |<7C>& <04> <00> & <04> <00>b& <04> <00><>f <04> <00><><EFBFBD> <04> <00>3<EFBFBD> <04> <00><>(
=<3D><<3C>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MAC.scala
<0A>package MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MACBase extends Module {
|
|||
|
|
|
|||
|
|
class MACIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
7CA9882073A514DD01DF3046BE093A8F"
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A><package MAC
|
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|
|
|
|||
|
|
import chisel3._
|
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|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D0AC3A53A737689287208CFF922A712F#
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A><package MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D0AC3A53A737689287208CFF922A712F$ J<>u<EFBFBD>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ipackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Wire(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
reg Mdc;
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Counter[7:0] <= 8'h1;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
begin
|
|||
|
|
Counter[7:0] <= CounterPreset[7:0];
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
Counter[7:0] <= Counter - 8'h1;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Mdc <= 1'b0;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
Mdc <= ~Mdc;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign CountEq0 = Counter == 8'h0;
|
|||
|
|
assign MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
assign MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
B9632DD2069E2A36F8DBB5D818704D2A%
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Jpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
val Counter = RegInit( 1.U(7.W) )
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
reg Mdc;
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Counter[7:0] <= 8'h1;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
begin
|
|||
|
|
Counter[7:0] <= CounterPreset[7:0];
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
Counter[7:0] <= Counter - 8'h1;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Mdc <= 1'b0;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
Mdc <= ~Mdc;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign CountEq0 = Counter == 8'h0;
|
|||
|
|
assign MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
assign MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
5869C959B2F7B69B374FA69D8A65D027& I<><49>{
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ipackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
val Mdc = RegInit(false.B)
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
Mdc <= 1'b0;
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(CountEq0)
|
|||
|
|
Mdc <= ~Mdc;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign CountEq0 = Counter == 8'h0;
|
|||
|
|
assign MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
assign MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
69355A28E6FA5D795A15124EC0444153'
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Hpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool()) // Output clock
|
|||
|
|
val MdcEn = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = Wire(Bool()) // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
reg [7:0] Counter;
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
|
|||
|
|
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc;
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc;
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
val Mdc = RegInit(false.B)
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
0823B26F5671228D3486B5AC445441A9( E<><45>e
|
|||
|
|
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Gpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
val Mdc = Reg(Bool())
|
|||
|
|
val MdcEn = Wire(Bool())
|
|||
|
|
val MdcEn_n = Wire(Bool())
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire CountEq0;
|
|||
|
|
wire [7:0] CounterPreset;
|
|||
|
|
wire [7:0] TempDivider;
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
output Mdc; // Output clock
|
|||
|
|
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
FA647E951B06401024CF35E3773EBAF2)
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Bpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait {
|
|||
|
|
input [7:0] Divider; // Divider for the host clock
|
|||
|
|
|
|||
|
|
// Connecting the Clock Generator Module
|
|||
|
|
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
F8AB5FC5483E7A72A4466DA6EF2F1268* B[
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MACBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
F59C771AB4E0025F5D6F25E02A0050A4+
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: MACBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
9BE813A4BCA6824B13550221B17E45DE, B%<19>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
ED7D77B71BE8FC3C4AC656872990DDAD-
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Apackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
9AFD0DD23373DA3409CD63188718F6A8. U<><55>a
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ypackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
|||
|
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
|||
|
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
|||
|
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
|||
|
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
|||
|
|
endcase // case (ByteSelect[3:0])
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(LatchByte[0]){
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
always @ (posedge Clk or posedge Reset) begin
|
|||
|
|
if(Reset) begin
|
|||
|
|
ShiftReg[7:0] <= 8'h0;
|
|||
|
|
Prsd[15:0] <= 16'h0;
|
|||
|
|
LinkFail <= 1'b0;
|
|||
|
|
end else begin
|
|||
|
|
if(MdcEn_n) begin
|
|||
|
|
if(|ByteSelect) begin
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
|||
|
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
|||
|
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
|||
|
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
|||
|
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
|||
|
|
endcase // case (ByteSelect[3:0])
|
|||
|
|
/* verilator lint_on CASEINCOMPLETE */
|
|||
|
|
end else begin
|
|||
|
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
if(LatchByte[0]) begin
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
if(Rgad == 5'h01)
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
end else begin
|
|||
|
|
if(LatchByte[1])
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
610CCAA496FCB031A5030DE42047CBBF/
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(LatchByte[0]){
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
02C03E4689AD964763F5479A470D8C87 P<><50><EFBFBD>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte[0]){
|
|||
|
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
B56F227A545D2410BAB2A2E43825ECF3
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad == 5'h01){
|
|||
|
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
508D70D451D054C8B6825C4A57FB5ADD Qp
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail <= ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte[1]){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D5FAECA73D1FF939D74AA55086413D83
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
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import chisel3._
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import chisel3.util
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class MIIMIO extends Bundle{
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val mdi = Input( Bool()) // MII Management Data In
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val mdc = Output(Bool()) // MII Management Data Clock
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val mdo = Output(Bool()) // MII Management Data Output
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val mdoEn = Output(Bool()) // MII Management Data Output Enable
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}
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class MIIMBase extends Module{
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class MIIMIO extends Bundle{
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}
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}
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/** Connecting the Clock Generator Module */
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trait MIIMClockGen{ this: MIIMBase =>
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val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
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val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
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val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
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// Counter counts half period
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val Counter = RegInit( 1.U(8.W) )
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val Mdc = RegInit(false.B) // Output clock
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val CountEq0 = Counter === 0.U
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val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
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val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
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when( CountEq0 ) {
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Counter := CounterPreset
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} .otherwise{
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Counter := Counter - 1.U
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}
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// Mdc is asserted every other half period
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when(CountEq0) {
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Mdc := ~Mdc
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}
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}
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trait MIIMShiftReg{ this: MIIMBase =>
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module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
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LatchByte, ShiftedBit, Prsd, LinkFail);
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input Clk; // Input clock (Host clock)
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input Reset; // Reset signal
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input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
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input Mdi; // MII input data
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input [4:0] Fiad; // PHY address
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input [4:0] Rgad; // Register address (within the selected PHY)
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input [15:0]CtrlData; // Control data (data to be written to the PHY)
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input WriteOp; // The current operation is a PHY register write operation
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input [3:0] ByteSelect; // Byte select
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input [1:0] LatchByte; // Byte select for latching (read operation)
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output ShiftedBit; // Bit shifted out of the shift register
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output[15:0]Prsd; // Read Status Data (data read from the PHY)
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output LinkFail; // Link Integrity Signal
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val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
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val Prsd = RegInit(0.U(16.W))
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val LinkFail = RegInit(false.B)
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when(MdcEn_n){
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when(|ByteSelect) {
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/* verilator lint_off CASEINCOMPLETE */
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ShiftReg := Mux1H(Seq(
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ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
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ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
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ByteSelect === "h4".U -> CtrlData(15,8),
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ByteSelect === "h8".U -> CtrlData( 7,0),
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))
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} .otherwise{
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ShiftReg := Cat(ShiftReg(6,0), Mdi)
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when(LatchByte.extract(0)){
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Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
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when(Rgad === 1.U){
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LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
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}
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} .otherwise{
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when(LatchByte[1]){
|
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Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
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}
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}
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}
|
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}
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assign ShiftedBit = ShiftReg[7];
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}
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trait MIIM { This: MIIMBase=>
|
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input Clk; // Host Clock
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input Reset; // General Reset
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input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
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input [4:0] Rgad; // Register Address (within the PHY)
|
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input [4:0] Fiad; // PHY Address
|
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input NoPre; // No Preamble (no 32-bit preamble)
|
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|
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input WCtrlData; // Write Control Data operation
|
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input RStat; // Read Status operation
|
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input ScanStat; // Scan Status operation
|
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output Busy; // Busy Signal
|
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output LinkFail; // Link Integrity Signal
|
|||
|
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output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
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output [15:0] Prsd; // Read Status Data (data read from the PHY)
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output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
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output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
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output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
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// Generation of the EndBusy signal. It is used for ending the MII Management operation.
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val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
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val EndBusy = RegInit(false.B, EndBusy_d)
|
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// Update MII RX_DATA register
|
|||
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val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
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// Generation of the delayed signals used for positive edge triggering.
|
|||
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val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
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val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
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val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
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val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
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// Generation of the Start Commands (Write Control Data or Read Status)
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val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
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val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
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val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
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when( EndBusy ){
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|||
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WCtrlDataStart := false.B
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RStatStart := false.B
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} .otherwise{
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when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
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WCtrlDataStart := true.B
|
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|
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}
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when(RStat_q(1) & ~RStat_q(2)){
|
|||
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RStatStart := true.B
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}
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}
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// Generation of the Nvalid signal (indicates when the status is invalid)
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|||
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val Nvalid = RegInit(false.B)
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when( ~InProgress_q2 & InProgress_q3 ) {
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Nvalid := false.B
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} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
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Nvalid := true.B
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|||
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}
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|||
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// Signals used for the generation of the Operation signals (positive edge)
|
|||
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val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
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val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
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val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
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val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
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val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
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val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
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|||
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|||
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// Generation of the Operation signals
|
|||
|
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val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
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|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
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|
|||
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|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
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|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
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|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
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|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
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|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
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|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
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|
|||
|
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|
|||
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|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
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|
|||
|
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|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
ACDF4A199C119563A2B4A1BAAF6D250F Qā
|
|||
|
|
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .otherwise{
|
|||
|
|
when(LatchByte.extract(1)){
|
|||
|
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
7523BB18B49EE6BE7670C342F9B8C968
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd <= {ShiftReg(6:0), Mdi, Prsd(7,0)};
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
DB1461EFA2DA25B6BD9C10FD3CDEB7BF Q<15><>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi);
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
assign ShiftedBit = ShiftReg[7];
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
17AEF765ECF281E160C6D8FC41CC3CD3
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7);
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
C532740223E8669D42E1F2585F50DDB0 Qf<>
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7)
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
901853399035F923273ED2159A07865F
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Ppackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
|||
|
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Input clock (Host clock)
|
|||
|
|
input Reset; // Reset signal
|
|||
|
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
input Mdi; // MII input data
|
|||
|
|
input [4:0] Fiad; // PHY address
|
|||
|
|
input [4:0] Rgad; // Register address (within the selected PHY)
|
|||
|
|
input [15:0]CtrlData; // Control data (data to be written to the PHY)
|
|||
|
|
input WriteOp; // The current operation is a PHY register write operation
|
|||
|
|
input [3:0] ByteSelect; // Byte select
|
|||
|
|
input [1:0] LatchByte; // Byte select for latching (read operation)
|
|||
|
|
|
|||
|
|
output ShiftedBit; // Bit shifted out of the shift register
|
|||
|
|
output[15:0]Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
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|
|||
|
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|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire ShiftedBit;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Shift Register Module
|
|||
|
|
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
|
|||
|
|
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
|
|||
|
|
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
D35F9A0ED192B5EE763CCAE3EAFF641F M<><4D>U
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Dpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIM { This: MIIMBase=>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
F7A6846C1464BA401E14A3394F7F4047
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Tpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input InProgress; // Operation in progress
|
|||
|
|
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
input [6:0] BitCounter; // Bit Counter
|
|||
|
|
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
output Mdo; // MII Management Data Output
|
|||
|
|
output MdoEn; // MII Management Data Output Enable
|
|||
|
|
|
|||
|
|
wire SerialEn;
|
|||
|
|
|
|||
|
|
reg MdoEn_2d;
|
|||
|
|
reg MdoEn_d;
|
|||
|
|
reg MdoEn;
|
|||
|
|
|
|||
|
|
reg Mdo_2d;
|
|||
|
|
reg Mdo_d;
|
|||
|
|
reg Mdo; // MII Management Data Output
|
|||
|
|
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Mdo signal.
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= 1'b0;
|
|||
|
|
Mdo_d <= 1'b0;
|
|||
|
|
Mdo <= 1'b0;
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(MdcEn_n)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= ~SerialEn & BitCounter<32;
|
|||
|
|
Mdo_d <= ShiftedBit | Mdo_2d;
|
|||
|
|
Mdo <= Mdo_d;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
19C3E34B90072569B36126BE14BFC1FD r⤫
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Tpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input InProgress; // Operation in progress
|
|||
|
|
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
input [6:0] BitCounter; // Bit Counter
|
|||
|
|
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
output Mdo; // MII Management Data Output
|
|||
|
|
output MdoEn; // MII Management Data Output Enable
|
|||
|
|
|
|||
|
|
wire SerialEn;
|
|||
|
|
|
|||
|
|
reg MdoEn_2d;
|
|||
|
|
reg MdoEn_d;
|
|||
|
|
reg MdoEn;
|
|||
|
|
|
|||
|
|
reg Mdo_2d;
|
|||
|
|
reg Mdo_d;
|
|||
|
|
reg Mdo; // MII Management Data Output
|
|||
|
|
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Mdo signal.
|
|||
|
|
always @ (posedge Clk or posedge Reset)
|
|||
|
|
begin
|
|||
|
|
if(Reset)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= 1'b0;
|
|||
|
|
Mdo_d <= 1'b0;
|
|||
|
|
Mdo <= 1'b0;
|
|||
|
|
end
|
|||
|
|
else
|
|||
|
|
begin
|
|||
|
|
if(MdcEn_n)
|
|||
|
|
begin
|
|||
|
|
Mdo_2d <= ~SerialEn & BitCounter<32;
|
|||
|
|
Mdo_d <= ShiftedBit | Mdo_2d;
|
|||
|
|
Mdo <= Mdo_d;
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Connecting the Output Control Module
|
|||
|
|
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
|
|||
|
|
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
|
|||
|
|
.Mdo(Mdo), .MdoEn(MdoEn)
|
|||
|
|
);
|
|||
|
|
}
19C3E34B90072569B36126BE14BFC1FD
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Gpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends Bundle{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
val SerialEn = WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & NoPre ))
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
}
A01F248A627C8354F09F9FFE36732D98
8/workspaces/RISCV-MAC-SWICH/src/main/scala/mac/MII.scala
<0A>Gpackage MAC
|
|||
|
|
|
|||
|
|
import chisel3._
|
|||
|
|
import chisel3.util
|
|||
|
|
|
|||
|
|
class MDIO extends Bundle{
|
|||
|
|
val mdi = Input( Bool()) // MII Management Data In
|
|||
|
|
val mdc = Output(Bool()) // MII Management Data Clock
|
|||
|
|
val mdo = Output(Bool()) // MII Management Data Output
|
|||
|
|
val mdoEn = Output(Bool()) // MII Management Data Output Enable
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
class MIIMBase extends Module{
|
|||
|
|
class MIIMIO extends MDIO{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/** Connecting the Clock Generator Module */
|
|||
|
|
trait MIIMClockGen{ this: MIIMBase =>
|
|||
|
|
val Divider = Wire( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0])
|
|||
|
|
|
|||
|
|
|
|||
|
|
val TempDivider = Mux( Divider < 2.U, 2.U, Divider ) // If smaller than 2
|
|||
|
|
val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Counter counts half period
|
|||
|
|
val Counter = RegInit( 1.U(8.W) )
|
|||
|
|
val Mdc = RegInit(false.B) // Output clock
|
|||
|
|
val CountEq0 = Counter === 0.U
|
|||
|
|
val MdcEn = CountEq0 & ~Mdc; // Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
val MdcEn_n = CountEq0 & Mdc; // Enable signal is asserted for one Clk period before Mdc falls.
|
|||
|
|
|
|||
|
|
when( CountEq0 ) {
|
|||
|
|
Counter := CounterPreset
|
|||
|
|
} .otherwise{
|
|||
|
|
Counter := Counter - 1.U
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Mdc is asserted every other half period
|
|||
|
|
when(CountEq0) {
|
|||
|
|
Mdc := ~Mdc
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIMShiftReg{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out
|
|||
|
|
val Prsd = RegInit(0.U(16.W))
|
|||
|
|
val LinkFail = RegInit(false.B)
|
|||
|
|
|
|||
|
|
when(MdcEn_n){
|
|||
|
|
when(|ByteSelect) {
|
|||
|
|
/* verilator lint_off CASEINCOMPLETE */
|
|||
|
|
ShiftReg := Mux1H(Seq(
|
|||
|
|
ByteSelect === "h1".U -> Cat("b01".U(2.W), ~WriteOp, WriteOp, Fiad(4,1)),
|
|||
|
|
ByteSelect === "h2".U -> Cat(Fiad.extract(0), Rgad(4,0), "b01".U(2.W)),
|
|||
|
|
ByteSelect === "h4".U -> CtrlData(15,8),
|
|||
|
|
ByteSelect === "h8".U -> CtrlData( 7,0),
|
|||
|
|
))
|
|||
|
|
} .otherwise{
|
|||
|
|
ShiftReg := Cat(ShiftReg(6,0), Mdi)
|
|||
|
|
when(LatchByte.extract(0)){
|
|||
|
|
Prsd := Cat(Prsd(15,8), ShiftReg(6,0), Mdi)
|
|||
|
|
when(Rgad === 1.U){
|
|||
|
|
LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet
|
|||
|
|
}
|
|||
|
|
} .elsewhen(LatchByte.extract(1)){
|
|||
|
|
Prsd := Cat(ShiftReg(6:0), Mdi, Prsd(7,0))
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
val ShiftedBit = ShiftReg.extract(7) // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
trait MIIMOutputCtl{ this: MIIMBase =>
|
|||
|
|
|
|||
|
|
// Generation of the Serial Enable signal (enables the serialization of the data)
|
|||
|
|
val SerialEn = WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & NoPre ) )
|
|||
|
|
| ~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & NoPre ))
|
|||
|
|
|
|||
|
|
val MdoEn = ShiftRegisters( SerialEn | InProgress & BitCounter<32.U, 3, false.B, en = MdcEn_n)
|
|||
|
|
val Mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, MdcEn_n)
|
|||
|
|
val Mdo_d = RegEnable( ShiftedBit | Mdo_2d, false.B, MdcEn_n)
|
|||
|
|
val Mdo = RegEnable( Mdo_d, false.B, MdcEn_n)
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
trait MIIM { this: MIIMBase =>
|
|||
|
|
|
|||
|
|
|
|||
|
|
input Clk; // Host Clock
|
|||
|
|
input Reset; // General Reset
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
|
|||
|
|
input [4:0] Rgad; // Register Address (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
|||
|
|
val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Start Commands (Write Control Data or Read Status)
|
|||
|
|
val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1) & ~WCtrlData_q(2) ){
|
|||
|
|
WCtrlDataStart := true.B
|
|||
|
|
}
|
|||
|
|
when(RStat_q(1) & ~RStat_q(2)){
|
|||
|
|
RStatStart := true.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Nvalid signal (indicates when the status is invalid)
|
|||
|
|
val Nvalid = RegInit(false.B)
|
|||
|
|
when( ~InProgress_q2 & InProgress_q3 ) {
|
|||
|
|
Nvalid := false.B
|
|||
|
|
} .elsewhen(ScanStat_q2 & ~SyncStatMdcEn) {
|
|||
|
|
Nvalid := true.B
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Signals used for the generation of the Operation signals (positive edge)
|
|||
|
|
|
|||
|
|
val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, en: MdcEn) // Start Write Control Data Command delayed 2 Mdc cycle
|
|||
|
|
val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, en: MdcEn) // Start Read Status Command delayed 2 Mdc cycles
|
|||
|
|
val InProgress_q = ShiftRegisters(InProgress, 3, false.B, en: MdcEn) // Operation in progress delayed 3 Mdc cycles
|
|||
|
|
val LatchByte0 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h3F".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte1 = ShiftRegisters(InProgress & ~WriteOp & BitCounter == "h37".U, 2, false.B, MdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
val LatchByte = Cat( LatchByte1, LatchByte0 ) // Latch Byte selects which part of Read Status Data is updated from the shift register
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the Operation signals
|
|||
|
|
val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected)
|
|||
|
|
val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected)
|
|||
|
|
val ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected)
|
|||
|
|
val StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp // Start Operation (start of any of the preceding operations)
|
|||
|
|
|
|||
|
|
// Busy
|
|||
|
|
val Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the InProgress signal (indicates when an operation is in progress)
|
|||
|
|
// Generation of the WriteOp signal (indicates when a write is in progress)
|
|||
|
|
val InProgress = RegInit(false.B) // Operation in progress
|
|||
|
|
val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress)
|
|||
|
|
|
|||
|
|
when(MdcEn){
|
|||
|
|
when(StartOp) {
|
|||
|
|
InProgress := true.B
|
|||
|
|
when( ~InProgress ){
|
|||
|
|
WriteOp := WriteDataOp
|
|||
|
|
}
|
|||
|
|
} .elsewhen(EndOp) {
|
|||
|
|
InProgress := false.B
|
|||
|
|
WriteOp := false.B
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
|
|||
|
|
val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter
|
|||
|
|
|
|||
|
|
when( MdcEn ){
|
|||
|
|
when( InProgress ) {
|
|||
|
|
when( NoPre & BitCounter === 0.U ) {
|
|||
|
|
BitCounter := "h21".U
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := BitCounter + 1.U
|
|||
|
|
}
|
|||
|
|
} .otherwise {
|
|||
|
|
BitCounter := 0.U
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Operation ends when the Bit Counter reaches 63
|
|||
|
|
val EndOp = BitCounter === 63.U // End of Operation
|
|||
|
|
val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
|
|||
|
|
|
|||
|
|
ByteSelect(0) := InProgress & ((NoPre & (BitCounter === 0.U)) | (~NoPre & (BitCounter === "h20".U)));
|
|||
|
|
ByteSelect(1) := InProgress & (BitCounter === "h28".U);
|
|||
|
|
ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U);
|
|||
|
|
ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U);
|
|||
|
|
|
|||
|
|
}
59287D518069D400D6FD3CB7C9FB943D WI{ "#$%&'( )
|
|||
|
|
* + ,
-./ <03>Jr
chunk.10chunk.11chunk.cchunk.dchunk.fmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:10,block:5c,len:47,liveMax:0,livePages:0,map:2a,max:55d20,pages:12,root:40001177e54,time:c60122,unused:c60208,unusedAtVersion:11,version:10,toc:46132,occupancy:ffff03<30>chunk:11,block:57,len:3,liveMax:2cd0,livePages:7,map:2a,max:32d0,pages:8,root:44000095d56,time:c601e9,unusedAtVersion:11,version:11,toc:298b,occupancy:80<38>chunk:c,block:5a,len:2,liveMax:0,livePages:0,map:28,max:18d0,pages:7,root:300000442d4,time:7fc045,unused:c601e9,unusedAtVersion:10,version:c,toc:1507,occupancy:7f<37>chunk:d,block:3,len:1,liveMax:0,livePages:0,map:2a,max:1130,pages:4,root:340000252d6,time:7fc2bc,unused:c601e9,unusedAtVersion:10,version:d,toc:dc4,occupancy:0f<30>chunk:f,block:2,len:1,liveMax:0,livePages:0,map:2a,max:580,pages:2,root:3c000008454,time:c18f8a,unused:c601e9,unusedAtVersion:10,version:f,toc:525,occupancy:031 44000073603 48000002c0b 44000002c18 48001124e86 4400001bbde 4400006d5ce 44000072e80 <07> , <07> Qd <07> <0F><> <07> "}<7D> <07> 4<>f <07> F]<5D> <07> V<><56> <07> gm<67> <07> |<7C>& <07> <00> & <07> <00>b& <07> <00><>f <07> <00><><EFBFBD> <07> <00>3<EFBFBD> <07> <00><>( N<> dTStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
|||
|
|
val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
|||
|
|
val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
|
|||
|
|
|
|||
|
|
when( EndBusy ){
|
|||
|
|
WCtrlDataStart := false.B
|
|||
|
|
RStatStart := false.B
|
|||
|
|
} .otherwise{
|
|||
|
|
when( WCtrlData_q(1)chunk:12,block:51,version:12,fletcher:538ece96
|
|||
|
|
chunk:14,block:96,len:1,map:2a,max:600,next:97,pages:1,root:50000002c16,time:c6022b,version:14,toc:605
|
|||
|
|
U<05> chunk.10chunk.11chunk.12chunk.13chunk.cchunk.dchunk.fmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:10,block:9,len:47,liveMax:0,livePages:0,map:2a,max:55d20,pages:12,root:40001177e54,time:c60122,unused:c60208,unusedAtVersion:11,version:10,toc:46132,occupancy:ffff03<30>chunk:11,block:4,len:3,liveMax:2cd0,livePages:7,map:2a,max:32d0,pages:8,root:44000095d56,time:c601e9,unusedAtVersion:11,version:11,toc:298b,occupancy:80<38>chunk:12,block:51,len:45,liveMax:54120,livePages:10,map:2a,max:54520,pages:11,root:48001126454,time:c60208,unusedAtVersion:12,version:12,toc:44d86,occupancy:000001<30>chunk:13,block:50,len:1,liveMax:0,livePages:0,map:2a,max:600,next:51,pages:1,root:4c000002c16,time:c6021b,unused:c6022b,unusedAtVersion:13,version:13,toc:557,occupancy:01<30>chunk:c,block:7,len:2,liveMax:0,livePages:0,map:28,max:18d0,pages:7,root:300000442d4,time:7fc045,unused:c601e9,unusedAtVersion:10,version:c,toc:1507,occupancy:7f<37>chunk:d,block:3,len:1,liveMax:0,livePages:0,map:2a,max:1130,pages:4,root:340000252d6,time:7fc2bc,unused:c601e9,unusedAtVersion:10,version:d,toc:dc4,occupancy:0f<30>chunk:f,block:2,len:1,liveMax:0,livePages:0,map:2a,max:580,pages:2,root:3c000008454,time:c18f8a,unused:c601e9,unusedAtVersion:10,version:f,toc:525,occupancy:031 44000073603 48000002c0b 44000002c18 48001124e86 4400001bbde 4400006d5ce 44000072e80 ,dress (within the PHY)
|
|||
|
|
input [4:0] Fiad; // PHY Address
|
|||
|
|
input NoPre; // No Preamble (no 32-bit preamble)
|
|||
|
|
input WCtrlData; // Write Control Data operation
|
|||
|
|
input RStat; // Read Status operation
|
|||
|
|
input ScanStat; // Scan Status operation
|
|||
|
|
|
|||
|
|
output Busy; // Busy Signal
|
|||
|
|
output LinkFail; // Link Integrity Signal
|
|||
|
|
output Nvalid; // Invalid Status (qualifier for the valid scan result)
|
|||
|
|
|
|||
|
|
output [15:0] Prsd; // Read Status Data (data read from the PHY)
|
|||
|
|
|
|||
|
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
|
|||
|
|
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
|
|||
|
|
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
|
|||
|
|
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
|
|||
|
|
wire MdcEn_n;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
|
|||
|
|
val EndBusy_d = RegNext(false.B, ~InProgress_q2 & InProgress_q3)
|
|||
|
|
val EndBusy = RegInit(false.B, EndBusy_d)
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Update MII RX_DATA register
|
|||
|
|
val UpdateMIIRX_DATAReg = RegInit(false.B, EndBusy & ~WCtrlDataStart_q) // Updates MII RX_DATA register with read data
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
// Generation of the delayed signals used for positive edge triggering.
|
|||
|
|
val WCtrlData_q = ShiftRegisters(WCtrlData, 3, false.B, en: true.B)
|
|||
|
|
val RStat_q = ShiftRegisters(RStat, 3, false.B, en: true.B)
|
|||
|
|
val ScanStat_q = ShiftRegisters(ScanStat, 2, false.B, en: true.B)
|
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val SyncStatMdcEn = RegEnable(ScanStat_q(1), false.B, enable = MdcEn) // Scan Status operation delayed at least cycles and synchronized to MdcEn
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// Generation of the Start Commands (Write Control Data or Read Status)
|
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val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected)
|
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val WCtrlDataStart_q = RegEnable(WCtrlDataStart, false.B, enable= ~EndBusy)
|
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val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected)
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when( EndBusy ){
|
|||
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WCtrlDataStart := false.B
|
|||
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chunk:14,block:96,version:14,fletcher:71c2d39e
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chunk:15,block:97,len:2,map:2c,max:1b30,next:99,pages:5,root:54000040558,time:c60629,version:15,toc:161f
|
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|
|
<06>c 20b95b21377d660d5803b3f159a6a0715eaca19a5eb2888f5eb3a95877cea3368b8898848b890ce38b890d138b8910958b8981428b8989028b8a011f8b8cd1e98d68a4f48fa25204a2f52e58da71dbdbe246eb63eabe0274f25aa7b7f4470498f4a56b5f582d64f#org.h2.mvstore.db.NullValueDataType#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.type.ByteArrayDataType,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory ,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory ,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory #org.h2.mvstore.db.NullValueDataType%org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory %org.h2.mvstore.db.RowDataType$Factory%org.h2.mvstore.db.RowDataType$Factory%org.h2.mvstore.db.RowDataType$Factory
|
|||
|
|
%org.h2.mvstore.db.RowDataType$Factory org.h2.mvstore.type.LongDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType2org.h2.mvstore.db.LobStorageMap$BlobReference$Type,org.h2.mvstore.tx.VersionedValueType$Factory%org.h2.mvstore.db.RowDataType$Factory
|
|||
|
|
-org.h2.mvstore.db.LobStorageMap$BlobMeta$Type#org.h2.mvstore.db.NullValueDataType,org.h2.mvstore.tx.VersionedValueType$Factory#org.h2.mvstore.db.NullValueDataType "A @ <01> @ x map.f H<01> map.10map.11map.12map.13map.14map.15map.16map.17map.18map.19map.1amap.1bmap.1cmap.1dmap.1emap.1fmap.2map.20map.2bmap.2cmap.3map.5map.6map.7map.8map.9map.bmap.cmap.e7name:table.10,createVersion:1,key:8fa25204,val:5eb2888f7name:index.11,createVersion:1,key:8b890ce3,val:da71dbdb7name:table.13,createVersion:1,key:8fa25204,val:5eaca19a7name:table.14,createVersion:1,key:8fa25204,val:5eaca19a7name:table.15,createVersion:1,key:8fa25204,val:5eb3a9587name:index.16,createVersion:1,key:8b889884,val:da71dbdb7name:table.18,createVersion:1,key:8fa25204,val:5eaca19a7name:index.19,createVersion:1,key:8b898142,val:da71dbdb7name:table.21,createVersion:1,key:8fa25204,val:5eb2888f7name:index.23,createVersion:1,key:8b890d13,val:da71dbdb7name:index.25,createVersion:1,key:8b891095,val:da71dbdb7name:table.27,createVersion:1,key:8fa25204,val:5eaca19a7name:index.28,createVersion:1,key:8b898902,val:da71dbdb7name:index.30,createVersion:1,key:8d68a4f4,val:da71dbdb7name:index.32,createVersion:1,key:8b898902,val:da71dbdb7name:table.33,createVersion:1,key:8fa25204,val:5803b3f1name:_7name:index.35,createVersion:1,key:8b8a011f,val:da71dbdb name:undoLog.1,createVersion:14 name:undoLog.2,createVersion:14name:openTransactions&name:table.0,key:8fa25204,val:5803b3f1%name:lobMap,key:8fa25204,val:f4470498)name:tempLobMap,key:8fa25204,val:59a6a071$name:lobRef,key:eabe0274,val:f4a56b5&name:lobData,key:8fa25204,val:59a6a0716name:table.3,createVersion:1,key:8fa25204,val:f25aa7b76name:index.6,createVersion:1,key:8b8cd1e9,val:da71dbdb6name:table.7,createVersion:1,key:8fa25204,val:5eb2888f 5<0F> map.fname._
name.index.11
name.index.16
name.index.19
name.index.23
name.index.25
name.index.28
name.index.30
name.index.32
name.index.35 name.index.6 name.index.8 name.lobData name.lobMap name.lobRefname.openTransactions name.table.0
name.table.10
name.table.13
name.table.14
name.table.15
name.table.18
name.table.21
name.table.27 name.table.3
name.table.33 name.table.7name.tempLobMapname.undoLog.1name.undoLog.26name:index.8,createVersion:1,key:8b890ce3,val:da71dbdb2111517191a1c1d1e20cf968351012131416181bb1fe72b2c
|
|||
|
|
|
|||
|
|
chunk.10chunk.11chunk.12chunk.13chunk.14chunk.cchunk.dchunk.fmeta.idroot.1root.1froot.2root.20root.5root.broot.c<>chunk:10,block:9,len:47,liveMax:0,livePages:0,map:2a,max:55d20,pages:12,root:40001177e54,time:c60122,unused:c60208,unusedAtVersion:11,version:10,toc:46132,occupancy:ffff03<30>chunk:11,block:4,len:3,liveMax:19a0,livePages:3,map:2a,max:32d0,pages:8,root:44000095d56,time:c601e9,unusedAtVersion:14,version:11,toc:298b,occupancy:f1<66>chunk:12,block:51,len:45,liveMax:54120,livePages:10,map:2a,max:54520,pages:11,root:48001126454,time:c60208,unusedAtVersion:12,version:12,toc:44d86,occupancy:000001<30>chunk:13,block:50,len:1,liveMax:0,livePages:0,map:2a,max:600,next:51,pages:1,root:4c000002c16,time:c6021b,unused:c6022b,unusedAtVersion:13,version:13,toc:557,occupancy:01<30>chunk:14,block:96,len:1,liveMax:0,livePages:0,map:2a,max:600,next:97,pages:1,root:50000002c16,time:c6022b,unused:c60629,unusedAtVersion:14,version:14,toc:605,occupancy:01<30>chunk:c,block:7,len:2,liveMax:0,livePages:0,map:28,max:18d0,pages:7,root:300000442d4,time:7fc045,unused:c601e9,unusedAtVersion:10,version:c,toc:1507,occupancy:7f<37>chunk:d,block:3,len:1,liveMax:0,livePages:0,map:2a,max:1130,pages:4,root:340000252d6,time:7fc2bc,unused:c601e9,unusedAtVersion:10,version:d,toc:dc4,occupancy:0f<30>chunk:f,block:2,len:1,liveMax:0,livePages:0,map:2a,max:580,pages:2,root:3c000008454,time:c18f8a,unused:c601e9,unusedAtVersion:10,version:f,toc:525,occupancy:031 5400001dd83 48000002c0b 54000002c18 48001124e86 4400001bbde 4400006d5ce 44000072e80 <00> , @ ݃ @ <01> @ x X chunk:15,block:97,version:15,fletcher:77ced4a0
|