eb001/src/main/scala/backBoard/shin/SRAMFifo.scala

package BACK

import chisel3._
import chisel3.util._

class SRAM2kWRIO extends Bundle {
  val addrw = Output(UInt(11.W))
  val dataw = Output( UInt(8.W) )
  val enw   = Output(Bool())
}

class SRAM2kRDIO extends Bundle {
  val addrr = Output(UInt(11.W))
  val datar = Input( UInt(8.W) )
  val enr   = Output(Bool())
}


class SRAM2kIO extends Bundle {
  val addrr  = Output(UInt(11.W))
  val addrw  = Output(UInt(11.W))

  val dataw = Output( UInt(8.W) )
  val datar = Input( UInt(8.W) )
  val enw   = Output(Bool())
  val enr   = Output(Bool())
}

class SRAM2kFifoIO extends Bundle {
  val sram = new SRAM2kIO

  val enq = Flipped(Decoupled(UInt(8.W)))
  val deq = Decoupled(UInt(8.W))
}

class SRAM2kFifo extends Module {
  val io: SRAM2kFifoIO = IO(new SRAM2kFifoIO)

  val wptr = RegInit(0.U((11+1).W))
  val rptr = RegInit(0.U((11+1).W))

  val isFull  = (wptr.extract(11) =/= rptr.extract(11)) & (wptr(10,0) === rptr(10,0))
  val isEmpty = (wptr === rptr)


  io.sram.addrr := rptr(10,0)
  io.sram.addrw := wptr(10,0)

  io.sram.dataw := io.enq.bits
  io.deq.bits := io.sram.datar
  io.sram.enw   := io.enq.fire
  io.sram.enr   := true.B

  io.enq.ready := ~isFull
  io.deq.valid := ~isEmpty

  when( io.enq.fire ){
    wptr := wptr + 1.U
  }

  when( io.deq.fire ){
    rptr := rptr + 1.U
  }

}