53 lines
1.0 KiB
Scala
53 lines
1.0 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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class SRAM2kIO extends Bundle {
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val addrr = Output(UInt(11.W))
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val addrw = Output(UInt(11.W))
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val dataw = Output( UInt(8.W) )
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val datar = Input( UInt(8.W) )
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val enw = Output(Bool())
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val enr = Output(Bool())
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}
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class SRAM2kFifoIO extends Bundle {
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val sram = new SRAM2kIO
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val enq = Flipped(Decoupled(UInt(8.W)))
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val deq = Decoupled(UInt(8.W))
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}
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class SRAM2kFifo extends Module {
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val io: SRAM2kFifoIO = IO(new SRAM2kFifoIO)
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val wptr = RegInit(0.U((11+1).W))
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val rptr = RegInit(0.U((11+1).W))
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val isFull = (wptr.extract(11) =/= rptr.extract(11)) & (wptr(10,0) === rptr(10,0))
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val isEmpty = (wptr === rptr)
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io.sram.addrr := rptr(10,0)
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io.sram.addrw := wptr(10,0)
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io.sram.dataw := io.enq.bits
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io.deq.bits := io.sram.datar
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io.sram.enw := io.enq.fire
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io.sram.enr := true.B
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io.enq.ready := ~isFull
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io.deq.valid := ~isEmpty
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when( io.enq.fire ){
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wptr := wptr + 1.U
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}
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when( io.deq.fire ){
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rptr := rptr + 1.U
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}
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}
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